IT Fundamentals: Memory Interleaving and Organization Assignment

This assignment solution for IT Fundamentals explores memory organization concepts, specifically focusing on memory interleaving. The solution explains high-order and low-order interleaving with examples, illustrating how these techniques enhance throughput. The assignment then delves into a practical problem involving a memory system composed of 32 chips, detailing the address structure and module organization when using both high-order and low-order interleaving methods. The solution provides a step-by-step breakdown of the calculations and representations for each interleaving type, including address structures, chip and offset calculations, and memory bank configurations. The document concludes with a list of relevant references.

Running head: IT FUNDAMENTALS
IT FUNDAMENTALS
Name of the Student:
Name of the University:
Author note:

1IT FUNDAMENTALS
ANSWER TO QUESTION a:-
The method which is used for increasing the throughput is termed as Memory
Interleaving. The basic requirement states about the memory system that gets split into
independent based banks and thus it implies it can answer read or write based requests and those
are independent in real.
There are 2 categories of recollection incorporating like High Order and the other is Low
Order.
High-Order Interleaving:-
The HOI is the procedure of transfer of address from one address bar to another address
bar. The collection of those address bar are then collected in the memory location. For the
purpose of HOI, high range bits are used in the Section organizations. According to the Section
address those bits are stored on the memory. This is a natural arrangement which is found within
the AA26-A27 bus lines (Xin et al., 2017). Those bus lines are sequenced in 4 memory Sections
in a sequence of 2to 4 decoder.
The high order bits are sequenced or maintain the sequence in a consecutive manner and
are stored within the same Section. Whenever the high order beats reach the boundary order line,
the stored data does not follows the sequenced data. The sequence beat that maintains the
sequence consecutively are known as the High order interleaving (Liu et al., 2016).
ADDRESS (M) SECTION
0-64 0
64-128 1
128-192 2

2IT FUNDAMENTALS
192-256 3
Low-Order Interleaving:-
LOI generally spreads the memory bits in the memory address and spreads the memory
bits in the memory location. This results in horizontal formatting sequenced in the Section
(Brock et al., 2018). This implies that the small Bits are used for the purpose of identification of
the Sections in the memory location. The High Order Bits that are displaced in the address bar
are stored in the Low Order Interleaving Section.

3IT FUNDAMENTALS
.
ADDRESS SECTION
0 0
1 1
2 2
3 3
4 0
5 1
6 2
7 3
8 0
9 1

4IT FUNDAMENTALS
LOW ORDER INTERLEAVING:-
No of Section 8 (Mo-M7) and
Memory bit: - 32
Address structure: - (Section structure)
EXAMPLE:-
HIGH ORDER INTERLEAVING:-
No of Section 8 (Mo-M7) and
Memory bit: - 32
Address structure (Section structure)
HIGH ORDER INTERLEAVING a b c d
SECTION 0 0 1 2 3
SECTION 1 4 5 6 7
SECTION 2 8 9 10 11
SECTION 3 12 13 14 15
SECTION 4 16 17 18 19
SECTION 5 20 21 22 23
SECTION 6 24 25 26 27
SECTION 7 28 29 30 31

5IT FUNDAMENTALS
LOW ORDER INTERLEAVING a b c d
SECTION 0 0 8 16 24
SECTION 1 1 9 17 25
SECTION 2 2 10 18 26
SECTION 3 3 11 19 27
SECTION 4 4 12 20 28
SECTION 5 5 13 21 29
SECTION 6 6 14 22 30
SECTION 7 7 15 23 31
ANSWER TO b:-
When the value of K is taken 4, the interleaving way results to be 16.
Let X be the interleaving method,
X= 2k
In this solution k =4 so, x is the 24= 16
For every arrangement, the k secondary location bits choose its own section (Michael &Gómez-
Barquero, 2016).
According to the problem, the number of bits becomes = (16*8= 128)
Then we say that (32*4k=128k)
Which implies, 128k= 27
Then, the Addressable unit calculated = (2^7*2^10) =2^ (10+7) =2^17
Therefore, seventeen bits are required for allocation of each location
According to the equation, the Memory banks will be 8= (23)
4k*8 (R0)
4k*8 (R1)
……………..

6IT FUNDAMENTALS
Which implies, each Section memory= (128/8=16)
Therefore the calculated Section memory is 16
which implies, 16= 24
So 4 bits offset Section
The bit number is (17-4=13 bits)
Therefore, for a HOI, the address memory organization can be represented as:
Chip (4) Offset chip(13)
0100 0000000001101
Therefore, For LOI, the address memory organization can be represented as:
Offset chip(13) Chip(4)
0001000010100 1101