ITC544 Assignment 1: Data Representation

This is a solved homework assignment for course ITC544, focusing on data representation and digital logic. The assignment includes problems on converting IEEE 754 single-precision floating-point numbers to decimal, working with different binary number representations (signed magnitude, one's co...Read More

Assignment 1: Data Representation and Digital Logic
ITC544
NAme:
ID:

1.
a. To convert floating point number represented by IEEE – 754 single precision format
to the decimal:
0 01111110 10100000000000000000000
Sign bit Exponent Mantissa
Positive number
Exponent --- 0*27 + 1*26 + 1*25 + 1*24 + 1*23 + 1*22 + 1*21 + 0*20
64 + 32 + 16 + 8 + 4 + 2
= 126
 126 – 127
-1
Mantissa --- 1.101
As the exponent is -1, therefore, number becomes 0.1101
0.1101 --- 0*20 + 1*2-1 + 1*2-2 + 0*2-3 + 1*2-4
0.5 + 0.25 + 0.0625
= 0.8125
Decimal number is 0.8125
b.
Binary number Decimal
Low High Low High
i. Signed
magnitude
01111 11111 -15 15
ii. One’s
Complement
10000 01111 -16 15
iii. Two’s
Complement
10001 01111 -17 15
2.
a. For the logic diagram, we have assumed that X denotes the input for 24-hour clock
timing and Y denotes the switch.
Y gives 1 as an input only when the time in 24-hour format is 9.00 to 12.00 or 13.00
to 16.00. For all other timings, 0 will be input.
Hence, the Boolean expression is:
X.Y = Z
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Logic Gate diagram:
Minimization:
No minimization is required. But if we assume that Y is always 1, i.e. switch is
always on, then expression
Z = X.1
Z = X
b. Prove that:
X’Y + XYZ’ + Y’ + XZ (Y+Y’) = 1
Considering L.H.S
 X’Y + XYZ’ + Y’ + XZ (Y+Y’)
 X’Y + Y’ + XYZ’ + XZ.1 (1 and 2)
 X’ + Y’ + XYZ’ + XZ (3 and 5)
 X’ + XZ + Y’ + XYZ’ (1)
 X’ + Z + Y’ + XZ’ (3)
 X’ + XZ’ + Z + Y’ (1)
 X’ + Z’ + Z + Y’ (3)
 X’ + 1 + Y’ (2)
 1
Hence Proved
Boolean Algebra Identities
1. Associative law A + B + C = A + C + B
2. Complementary law A + A’ = 1
3. Common Identity law A + A’B = A + B
5. Identity law A.1 = A
7. Null law 1 + A = 1
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