Computer Organisation and Architecture: Assignment 1

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ITC544
Computer Organisation and Architecture
Assignment 1
Data Representation & Digital Logic
Student Name: Lava Kumar Raikanapeta
Student ID: 11681520
Contents
Page 1 of 12

Question 1........................................................................................................................................3
Question 2........................................................................................................................................7
Question 3......................................................................................................................................11
List of Figures
Figure 1: Logic Diagram for NAND Gate.......................................................................................7
Figure 2: Logic diagram for NOR Gate...........................................................................................8
Figure 3: NOR as an INVERTER...................................................................................................8
Figure 4: Minimized Combinational Circuit.................................................................................10
Figure 5: X xor Y...........................................................................................................................11
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Question 1
A. 2ED1 to Binary
Hence according to 8421, hexadecimal, as well as octal numbers, can be converted into decimal.
Here 2 is converted to 0010, E is converted to 1110, D is converted to 1101 and 1 is to 0001. So
hexadecimal of 2ED1 is 0010111011010001.
B. -29.6610 to Binary
Ans. First of all taking the positive sign, for conversion of decimal numbers to binary, the
decimal number is divided by 2 progressively. The non-decimal part is divided by 2 and in next
iteration, quotient is divided by 2 and so on. The decimal part is multiplied by 2 and the resulting
non decimal is written in answer.
Division by 2 Quotient Remainder Bit no.
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29/2 14 1 0
14/2 7 0 1
7/2 3 1 2
3/2 1 1 3
1/2 0 1 4
So 29 is written as 111012.
For decimal part that is 0.66
Iteration Multiplied number Bit assigned Bit No.
0.66 * 2 1.32 1 1
0.32 * 2 0.64 0 2
0.64 * 2 1.28 1 3
0.28 * 2 0.56 0 4
0.56 * 2 1.12 1 5
So 0.66 is written as 1012. So 29.66 is written as 11101.101012. As this resulting binary number
starts with 1, so it represents that it is already a negative number. Hence -29.66 can be written as
11101.101012 in binary.
C. 1001111001102 to Hexadecimal
Ans. For conversion of Binary to Hexadecimal, starting from the least significant bit, 4 bits are
taken and the relative hexadecimal number is written for it. Again, from the given table:
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From least significant bit, taking 4 bits together:
10012 11102 01102 can be converted to 9E6. So 1001111001102 can be written as 9E6 in
Hexadecimal.
D. 11101110 (8-bit 2’s complement representation) to decimal
Ans. For taking 2’s complement, firstly the binary number is converted into 1’s complement. For
1’s complement, all the 1’s are changed to 0 and all 0’s changed to 1.
So 1’s complement is 00010001. Adding 1 to the resultant will give 2’s complement.
Table for Addition in Binary
Expression Sum Carry
0 + 0 0 0
0 + 1 1 0
1 + 0 1 0
1 + 1 0 1
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So, 00010001 + 00000001 = 00010010. This 2’s complement can be converted into decimal with
the help of given table.
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128 (27) 64 (26) 32 (25) 16 (24) 8 (23) 4 (22) 2 (21) 1 (20)
0 0 0 1 0 0 1 0
Taking the values from the table where 1 appears and adding them gives a Decimal number.
So 16 + 2 = 18. Hence 2’s complement of 11101110 can be written as 18 in decimal.
E. 1 01111110 11000000000000000000000
Ans. According to IEEE754, the binary number can be converted into a decimal by taking into
account the three parts i.e. sign 2exponent mantissa. So,
1 01111110 11000000000000000000000
Sign (-) 2exponent Mantissa
Step 1. As 1st bit is 1, so the resultant decimal number is negative.
Step 2. For calculating exponent, the decimal of given number is subtracted from bias.
128 (27) 64 (26) 32 (25) 16 (24) 8 (23) 4 (22) 2 (21) 1 (20)
0 1 1 1 1 1 1 0
So, decimal is 64+32+16+8+4+2= 126. Subtracting this decimal number from bias that is 127.
So 127-126= 1. So this 1 can be represented as a power of 2.
Step 3. Calculation of mantissa for 11000000000000000000000 is as follows:
1x2-1 + 1x2-2 + 0 + 0 + 0 + 0….. And so on. = 0.75
Hence according to IEEE754 this number can be written by:
(-1) sign bit * (1 + fraction) * 2bias – exponent = -1 * (1 + 0.75) * 2-1 = -1.75 * 2-1 = -0.875
Hence IEEE754 conversion of 1 01111110 11000000000000000000000 is -0.875.
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Question 2.
A.
Ans. Universal gates are defined as the gates through which any type of logic gates can be
designed. They can solve any type of a Boolean expression without need of any other gate.
Basically, these two universal gates are NAND and NOR gate.
1. NAND Gate: NAND gate represents the complement of AND Gate. It can also be said to be
NOT Gate behind AND Gate. For a two input NAND Gate, Logic symbol and truth table is
given below:
Figure 1: Logic Diagram for NAND Gate
Truth Table:
2. NOR Gate: NOR Gate represents the complement of OR Gate. It can also be said to be NOT
Gate behind OR Gate. For a two input NOR Gate, logic diagram and truth table are given below:
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Figure 2: Logic diagram for NOR Gate
Truth table:
For designing an inverter, any of the logic gates has been used. Taking example of NOR Gate, if
the two inputs shorted to one input and A is applied to that input, then the output will be
complement of A. Hence, NOR Gate perform inversion in this way.
Figure 3: NOR as an INVERTER
Truth table for NOR as an INVERTER is:
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INPUT (A) OUTPUT (Y)
0 1
1 0
B.
Ans. As per question, Quiz is denoted by Q, Assignment by A, and Journal by J and if student is
passed, then pass by P. The truth table for the given condition can be drawn as
Q A J P
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
For realization of a logic circuit for this truth table, K-map known as Karnaugh Map is used in
which three inputs Q, A and J gives one output P.
Y A’, J’ A’, J A, J A, J’
Q’ 0 0 1 0
Q 0 1 1 1
Pairing is done in K-map according to a priority of mapping 8 1’s, then 4 1’s, then 2 1’s and then
only 1 1’s.
OUTPUT Y= AJ + QA + QJ = A(J+Q) + QJ
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Figure 4: Minimized Combinational Circuit
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Question 3.
Ans. The truth table for the given circuit is given as:
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
By using K-map, the minimized expression and logic circuit diagram can be obtained. As for
three inputs, K-map is given as:
F X’, Y’ X’, Y X, Y X, Y’
Z’ 0 1 0 1
Z 0 1 0 1
So, the expression from K-map will be obtained as F = X’Y + XY’ = X xor Y
Figure 5: X xor Y
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