Detailed Design, Analysis, and Configuration of Multistage Op-Amps

This report delves into the design of multistage operational amplifiers, crucial for achieving higher gain and improved input/output impedance control compared to single-stage amplifiers. It explores various configurations, including CE-CE, CE-CC, CC-CE, and CC-CC, highlighting their respective characteristics and suitability for different applications. The report also examines different coupling types such as RC coupling, transformer coupling, and direct coupling, detailing their advantages and disadvantages. Furthermore, it outlines the design specifications and provides a step-by-step analysis, including DC and AC analysis, bias calculations, and impedance considerations. The report emphasizes the importance of understanding transistor characteristics and approximations in the design process, providing a comprehensive overview of multistage amplifier design principles.

DESIGN OF MULTISTAGE OPERATIONAL AMPLIFIER
SNO CONTENT PG_NO
1 Multistage Amplifier 2
2 Configuration 2
3 Coupling types 6
4 Design Specifications 8
5 Frequency response of the Amplifiers 13
6 Result obtained 14
References 14

1. Multistage Amplifier:
The purpose of the Multistage Amplifier is due to the practical insufficiency of the single stage amplifier
although it could be a power or voltage amplifier. In the process of multistage amplifier, ac coupling
device couples the output of the first stage to the input of the succeeding stage. This coupling device
could be anything such as the transformer or the capacitor. This process of cascading several coupling
devices is known as Cascading. The one generic structure that is sufficiently used for the broad class of
application is by the operational Amplifier (op-amp) according to Neamen (156). The op-amp is capable
of performing several operation based on the external component configuration such as the addition,
subtraction, integration, differentiation and inverter performance. The absolute value could be
performed based on the non-linear components in the feedback network by estimating the exponent or
logarithmic value of input current or voltage and perform hysteresis or limiting functions. These
complicated operations seem to be very easy with the op-amp functional building block.
There are three fundamental stages of the amplifier are considered that are as follows (Sedra and Smith,
56):
 Differential amplifier input stage: This could amplify the difference among the two input signal
rather than considering single input signal.
 High voltage gain state: This is said to be the Common-Emitter amplifier.
 Low output impedance stage: This has the high current gain value and the voltage gain is less
than unity which is obviously a common-collector configuration (Salivahanan, 28).
In single stage amplifier, there is a limit in achieving the gain of the amplifier. The input and the out
impedance could also be limited in the single stage amplifier. A better control of input and output
impedance with the better gain performance could be made by the multistage amplifiers. The main
advantage of multistage amplifier is that they have a flexible input and output impedance and also
promotes larger gain value (Siddique et al. 67). Open loop and negative feedback are the two classes of
the multistage amplifier. The design process of the open loop is considered to be tedious and they are
very sensitive to environment s that the component variations could affect the accuracy. This drawback
is eradicated in the negative feedback and promotes better efficiency but they are very difficult to
understand. The Operation Amplifier (OP-AMP) is said to be the fundamental building block of the
negative feedback amplifier that has high voltage gain multistage open-loop amplifier (Samadi et al. 8)
PNP and NPN transistors are used in the design of the Multistage amplifier. In certain circuit, the
combination of both the circuit could highly reduce the impact of sensitivity caused due to the
temperature by cancelling the voltage drop of the base-emitter terminal. The voltage drop could be
caused due to the temperature drift that seems to be cancelled from the net result (both should be
subtracted). The optimum bias condition could be achieved by involving the PNP transistor followed by
the NPN transistor.
2. Configuration:
Common-emitter – common-emitter:

If the sufficient voltage gain needs to be very high then the CE – CE configuration could be adapted.
Figure 1: The multistage amplifier that involves the common CE – CE configuration
Common-emitter – common-collector
The output impedance could be sufficiently decreased in the case of CE – CC configuration
Figure 2: The multistage amplifier that involves the common CE – CE configuration

Common-collector – common-emitter:
This configuration could sufficiently increase the input impedance due to the CC configuration circuit. An
important thing to be noted is that the right side of the figure could consist of the PNP transistor
followed by the NPN transistor (Goswami, et al. 5). In this case the temperature effect could be
significantly cancelled that gives a better performance of analysis (MacLean, 15).
(A) (B)
Figure 3: The multistage amplifiers that involves the common CC – CE configuration (A) NPN
followed by a NPN transistor (B) PNP followed by NPN transistor
Common-collector – common-collector:
In this configuration, the current gain could be very gain but the voltage gain could be less that unity due
to the Common Collector configuration (Ciofi, 40). As motioned in the previous case, there could be
better temperature insensitivity, which could enhance the performance. Moreover, the output
impedance could be very low followed by higher input impedance.

(A) (B)
Figure 4: The multistage amplifiers that involves the common CC – CC configuration (A) NPN followed by
a NPN transistor (B) PNP followed by NPN transistor
The below table describes the general characteristics of the Multistage amplifier
Table 1: Multistage amplifier general characteristics (Shekhar et al, 11)
Stage 1 Stage 2 Stage 3 Stage 4 Rin Rout Voltage gain
CE CE Medium Medium High
CE CC Medium Low Medium
CC CE High Medium Medium
CC CC Very high Very low <1
CE CE CE Medium Medium Extremely
high
CE CE CC Medium Low Very high
CE CC CE Medium Medium Very high
CE CC CC Medium Very Low Medium
CC CE CE High Medium Very high
CC CE CC High Low Medium
CC CC CE Very high Medium Medium
CC CC CC Very high Very low <1
CC CE CE CC High Low Very high
Description:
 Low – Less than few hundred ohms
 Medium – A few hundred to thousand ohms
 High - A few thousand to several ten thousand ohms

 Very high – A several ten thousand ohms
 Extremely high – A several hundred thousand ohms
3. Coupling types:
Cascading the transistors is said to be done by several methodology based on the user convenience.
(Dale, 8) There are four basic coupling types:
Resistance-Capacitance Coupling:
The simple resistance and the capacitance circuit could form the RC coupling circuit. The coupling
element used here is the capacitor that could block the DC and permits AC (Bruun, 78). This is one of the
most commonly used discrete amplifiers and it is found to be cheap and the frequency response could
be satisfactory. The amplifiers using this coupling scheme are said to be known as the RC coupled
amplifiers.
Figure 5: RC Coupling amplifiers (Cc is the coupling capacitance that block DC and permits AC)
Transformer Coupling:
The coupling device that includes the transformer at their intermediate stages is said to be known as the
transformer coupling (Ballentine, 10). The transformer could directly send the AC component to the
second stage and hence the capacitor is not necessary. The base return path could be offered by the
secondary winding and hence there is no necessary for the base resistance (Comer, 34). The impedance
matching could be done perfectly and also the efficiency could be better with this coupling that could
enhance the usage of this type of coupling device.

Figure 6: A circuit configuration that has the coupling transformer at their intermediate stages
Direct Coupling:
When there is a direct connection among the amplifier stages then it is said to be known as the Direct
Coupling (Charalampidis et al. 45). The design of the individual amplifier stage bias condition makes the
preceding stages to be directly connected without any DC isolation. This method could be mostly
adopted when there is a series load connection with the circuit connection in the output terminal. This
method finds its application in the loud speakers, head phones etc (Yahya, 108).
Figure 7: A circuit configuration that are directly coupled in their intermediate stages

4. Design Specifications:
Figure 8: Design that is based on CC – CE – CC configuration
The performance and the necessary calculations should be done by taking the individual single stage
amplifier by identical methods starting from the input stage of the configuration (Gajjar et al. 34).
Confusion arises at the point when the resistance of the collector circuit becomes the base resistance at
the next stage. Certain modification in calculation should be done while processing the common
collector stage since these amplifiers tends to vary by the external impedances. Necessary
approximations should be made at the calculation stage. First and foremost, the multistage circuit
configuration should be split into individual stages of single stage amplifier (Haojie et al. 86). The DC
analysis could be made initially followed by the AC analysis by breaking the configuration as stage 1,
stage 2 etc. (opened temporarily). Then the calculation of emitter and collector current is necessary.
The estimated parameters are considered to be the following
VCC = 15 V, RB1 = 220K, RB2 = 36K, RE1 = 1K, RE2A = 2 K, RE2B = 100 Ohms, RC2 = 6.8K, RE3 = 1K, C1 =
0.1 uF, C2 = 10 uF, C3 = 0.1 uF, Q1 = 2N3906, Q2 = 2N3904, Q3 = 2N3906.
VBE = 0.65 volt, β = 200
For the calculation, first let’s consider from the input of the amplifier and then work entirely step by step
till the output. The bias voltage, input and output impedance could be estimated from the given data:
Power supply: +15 V with respective to the ground
Quiescent current drawn from the power supply: Less than 8 mA

No load gain (1KHz): |Av| = 50 (±10%)
Number of transistors: Not more than 3
Resistance Value: Less than 220 KOhm (E24 series)
Source Resistance (Rs): 600 Ohm
Load Resistance: 1 KΩ
Bias Analysis of First Stage:
Initially Q1 bias condition should necessarily be calculated. The VBB1 is computed for the base circuit
with the open circuit voltage (Pulakka et al. 60). This is said to be
VBB1 = (Vcc * RB2) / (RB1 * RB2)
VBB1 = 15 * 220000 / (220000 + 36000) = 2.10 volts.
Then RB_Q1 is calculated by,
RB_Q1 = RB1 || RB2
RB_Q1 = 36K || 220K = 26.75K
We are not aware of the characteristic of the emitter circuit that is directly coupled in stage 2. Unless we
make a simplified approximation in stage 1, the CC amplifier at stage 1 is very difficult to analyze. The
loading bias at the succeeding stage of the well designed amplifier seems to be very small (Mahato, and
Kandarpa, 8). There will be a minimum dependency on the characteristics of the particular transistor in a
well-designed system. To verify the bias calculation the results could be used to again calculate the bias
condition of stage 1. If the obtained answer does not change much with the previously obtained result
then the approximation made is perfect.
Stage 2 could be ignored and stage 1 emitter current could be determined by the following:
IE1 = (-VB – VCC + VBE) / (RE1 + (RB_Q1 / β + 1)
IE1 = (1.364 –15 + 0.65) / (18K + 32.73K/151) = -0.0108 A.
The power supply of VEE is considered to be 15 Volt. We have added the VBE voltage of 0.65 since the
given transistor is PNP.
Now the base voltage at the transistor 2 could be calculated,
VB2 = VCC – (IE1 * RE1)
VB2 = 15 – 0.0108 A * 1K = 4.2 volts

The voltage relative to the base at Q1 seems to be higher than that of the open circuit voltage since the
PNP base current will be out of the transistor. Now the base voltage of the Q1 transistor could be
calculated as,
VB1 = VB2 - VBE
VB1 = 4.2 – 0.65 = 3.55 volts.
Stage 2:
The bias voltage for the stage 1 had been calculated. Now the effective resistance for the stage 2 should
be calculated. This value in this case should be smaller than the Q1 effective resistance. Here RE1 is
considered to be parallel with the base resistance that should be divided by the factor β + 1
RB_Q2 = RE1 || (RBQ1 / β + 1)
RB_Q2 = 1,000 || 133.08 = 117 ohms
This value is found to be very small when compared to the emitter resistance RE2 for the well-designed
amplifier. Hence, it is said that the base current of Q2 is found to be very small under the bias condition.
This could be assumed at first itself. If this is not the case in the calculation, then the resistance value
should be changed and the calculation should be done at necessary intervals of iteration. The calculation
could include the value of RB_Q2 that is also found to be very small.
IE2 = (VB2 – VBE) / (RE2A + (RB_Q2 / β+1))
IE2 = (4.2 – 0.65) / ( 2 K + 117 / 201) = 1.77 mA
The base voltage found at Q1 is said to be same as the emitter voltage at Q2. This circuit is considered to
be independent of the temperature practically due to the combination of PNP and NPN that could yield
a better result. The bias condition at the collector terminal of Q2 is calculated. This is done by
multiplying the emitter current of Q2 with the β / β+1.
IC2 = IE2 * (β / β+1)
IC2 = 1.77 mA.
Stage 3:
The collector terminal at Q2 for the open circuit could be calculated at this stage. Until the bias
condition of Q3 is not known, we could not be able to determine the bias condition. The VBB of Q# is
said to be same as that of the VC2 according to the thevenin voltage rule. The collector terminal of Q2
will appear as the current source and so the collector resistance of Q2 is the RB of Q3. Otherwise it could
also be termed as the infinite resistance.
VB_Q3 = VCC- (IC2 * RC2)

VBB_Q3 = 15 – (1.76 mA * 1 K) = -2.6 volts
Now the emitter current for the Q3 transistor should be calculated,
IE3 = (VB_Q3 – VCC + VBE)/ (RE3 + (RC2 / β +1)
IE3 = (-2.6 - 15 + 0.65) / (1000 + 6.8 K / 201) = -0.0163 A
The emitter voltage of Q3 with respect to ground is
VE3 = VCC – (IE3 * RE3)
VE3 = 15 – (16.3 mA * 1 K) = -1 volts
The open circuit voltage will be less when compared with the base voltage (Mahato and Kandarpa in
Stability of Feedback Based LNA Topologies for UWB Communication, 78) and the VB3 could be
calculated as,
VB3 = VE3 – VBE
VB3 = -1 – 0.65 = -1.65 volts
AC analysis:
The above is said to be the end of the bias calculation (Vandamme, E. P. and Vandamme, L.K.J, 89). Now
the dynamic resistance could be considered under the AC analysis
re1 = 0.026 / 0.01018 A = 2.4074 ohms
re2 = 0.026 / 1.77 mA = 14.68 ohms
re3 = 0.026 / 0.016 A = 1.625 ohms
The resistance values are calculated from the emitter current of Q1, Q2 and Q3.
Input impedance calculation:
For calculating the input resistance, the emitter impedance of circuit one in the common collector mode
should be known. Here RE1 is found to be parallel with the stage 2, input impedance. Therefore we are
going to calculate the input impedance at the second stage,
rbt2 = (β + 1) (re2 + RE2A || RE2B)
rbt2 = 201 * (14.68 + 2200 || 100) = 16.3 K
Then the first stage input impedance could be calculated as,
rbt1 = (β + 1) (re1 + RE1 || rbt2)

rbt1 = 201 * (2.4074 + 1000 || 22093) = 192.77 K
The net input impedance is found to have a parallel connection and therefore,
Rin = RB_Q1 || rbt1
Rin = 26750 || 192770 = 23.49 KOhm.
Output impedance Calculation:
The output resistance of the CC stage at the output side is said to be the output resistance of the
amplifier that is estimated by
Ro = RE3 || (re3 + (RC2 / β+1))
Ro = 1000 || (1.625 + 6.8 K / 201) = 29.48 ohms
Unloaded Voltage gain |Av| of the amplifier:
The voltage gain at stage 1 is said to be,
Av1 = RE1 / (re1 + RE1)
Av1 = 1 K / (2.4074 + 1 K) = 0.997
The source resistance could be calculated by the emitter resistance and the effective resistance of Q1.
But according to the given condition, the source resistance is said to be 600 ohm. Hence, this value
could be used to calculate the voltage division factor of the first and the second stage,
Vd12 = rbt2 / (Rs + rbt2)
Vd12 = 192.77 K / (600 + 192.77 K) = 0.996
The voltage gain of the second stage is
Av2 = (β / β + 1) * (RC2 / re2 + (RE2A || Re2B)
Av2 = (200 / 201) * (6.8 K / (14.68 + 95.23) )= 50.69
The input resistance of the third stage is calculated as,
Rin3 = (β + 1) * (re3 + RE3)
Rin3 = 201 * (1.625 + 1000) = 201.32 K
Now the voltage division factor of the second and the third stage is calculated,
Vd23 = 201.32 K / (6.8 K + 201.32 K) = 0.9729
The voltage gain of the third stage is