TMA3: Programmable Logic Controllers Assignment Solutions

This document presents a comprehensive solution to a Programmable Logic Controller (PLC) assignment. The solution addresses various aspects of PLC programming and related concepts. Question 1 focuses on designing ladder logic diagrams for momentary pushbuttons and timers, including off-delay timers and output designations. Question 2 involves the redesign of a Pelican crossing ladder diagram, including state transition diagrams and state equations. Question 3 delves into the use of shift registers for controlling relays, outlining the initialization and operational steps. Question 4 explores analog-to-digital (A/D) conversion, including step size calculations, hexadecimal conversions, and the impact of quantization errors, as well as a comparison of converters with different resolutions. Question 5 discusses multiplexing techniques, specifically analog multiplexing, including frequency division multiplexing (FDM) and wavelength division multiplexing (WDM). Question 6 involves circuit analysis using superposition theorem. Question 7 provides an overview of Local Area Networks (LANs), including types, applications, cable types, and the definition of Remote Terminal Units (RTUs), as well as the standards EIA-422 (RS-422) and IEEE-488. The assignment covers a wide range of topics related to PLC and electrical engineering principles.

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MODULE TITLE: PROGRAMMABLE LOGIC CONTROLLERS
TOPIC TITLES: PROGRAMMABLE FACILITIES AND
ADDITIONAL FACILITIES
TUTOR MARKED ASSIGNMENT 3

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Question 1
Design of the ladder logic
For the momentary pushbutton (Normally open)
push button1 → I 0.0
For the first timer with an off delay of 30 seconds,
Timer 1→ T1.0
The first output is designated by,
Output 1 →O0.0
For the second timer,
Timer 2→ T 2.0
The second output,
Output 2 →O0.1
The second push button (Normally connected)
Push button→ I0.1
The designed ladder diagram is presented below,

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Question 2
Redesign of the Pelican crossing ladder diagram,
The outputs are designated by L1 , L2 ,❑❑ ❑❑❑❑ L 3 , L 4 , L5 , L6 while the inputs are
represented by S1∧S2
State transition
LABEL No L1 L2 L3 L4 L5 L6 Transmission
line
Green E/W 1 1 0 0 0 0 1 S1
Yellow E/W 2 1 0 0 0 1 0 Delay
Green N/S 3 0 0 1 1 0 0 Delay
Yellow N/S 4 0 1 1 1 0 0 S2

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State equations,
ST1=(ST1 + ST4 ∙ TON1 (ST 4 , 4)) ∙(ST1 + S1 + S2 )
ST2=( ST2 + ST1−S1 S2 )∙( ST 2+TON 1 (ST 2))
ST3=(ST3 + ST2 ∙TON 1 (ST 2 , 4))∙( ST3 +S1 + S2 )
ST 4=(ST 4 +ST3 ∙ S1 ∙ S2) ∙( ST4 +TON2 (ST 4 , 4 ))

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Question 3
We are required to use two 8-bit shift registers. Each shift register takes 3 inputs and can
control 8 relays with its 8 outputs as shown in the figure below,
An initial start signal is required and thereafter, it can be free running. Assuming the initial
signal to be S, the start signal must have a duration less than that of a single clock cycle. The
signals to the control relays are represented by C50 to C57. The first shift register thus controls
8 relays from C50 to C57 while the second shift register controls the 7 relays from C60 to C66.
On initiating the start signal, the system begins from STEP 1 to STEP 15, then it has to go to
STEP 2.

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Question 4

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a)
First circuit
Resolution=10 bit
input range=0−5V
The step size will be,
5
210 = 5
1024 =4.88 mV /bit
The number of steps will be,
input voltage
step ¿ ¿ 2
5 /1024 =409.6 ≈ 410 ¿
410
2 205 0
2 102 1
2 51 0
2 25 1
2 12 1
2 6 0
2 3 0
2 1 1
2 0 1
110011010
Converting to hexadecimal,

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Result Remainder
19 A16410/16 25 10
25/16 1 9
1/16 0 1
Second circuit
resolution=12 bit
range=0−10 V
For a 2 V input, the digital output for the first circuit will be,
10
212 = 10
4096 =2.44 mV /bit
The number of steps will be,
input voltage
step ¿ ¿ 2
10 /4096 =819.2 ≈ 819 ¿
819
2 409 1
2 204 1
2 102 0
2 51 0
2 25 1
2 12 1
2 6 0

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2 3 0
2 1 1
2 0 1
1100110011
Converting to hexadecimal,
Result Remainder
33316819/16 51 3
51/16 3 3
3/16 0 3
b)
One of the reasons why a digital signal output of an A/D converter is rarely equivalent to the
input analog is due to the quantization process which introduces round off errors since it’s
just an approximation of the input signal.
c)
A typical A/D converter utilizes a single converter that has multiple channels for analog
signal conversion. The A/D converter utilizes a specific polling frequency on the input analog
signals (Pelgrom, 2013). Consequently, if we consider an A/D with only 4 channels, the
maximum on-time for any single channel is a quarter of the maximum switching rate of the
A/D multiplexer.
d)

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Of the two digital values in (a), the converter with a higher resolution (12 bits) has a
resolution twice that of the converter with a resolution of 10 bits. The converter with a
smaller step size is better at approximating the input signal, which reduces the quantization
error.
Question 5
Multiplexing is a technique that is used to combine multiple signals into a single signal, to be
transmitted over a shared medium (Sayana, & Zhuang, 2013). Specifically, analog
multiplexing involves the combining of analog signals. In analog multiplexing, the signals
can be combined according to their frequencies (frequency division multiplexing, FDM) or
according to their wavelengths in wavelength division multiplexing (WDM). In FDM,
frequency modulation is used to convert the signals into their respective frequency bands
using a certain carrier frequency after which a multiplexer combines the signals. The same
channel is used by all users but at different frequencies. In WDM, the electrical signals are
converted to light signals at different wavelengths. It is used for transmission through fiber
optic cables.
Question 6