Lab 4: State Machine Design

This practical assignment involves designing a state machine in Verilog to control a seven-segment display on a DE1-SoC FPGA. The state machine cycles through the digits of a five-digit number, with the direction of cycling controlled by a slider switch. A push button advances the display, and another acts as a reset. The assignment requires students to write synthesizable Verilog code (lab4_top.v), a testbench (lab4_top_tb.v), and a waveform file (lab4_wave.do) to simulate and verify their design. The design must handle changes in the slider switch direction during operation. The assignment provides detailed specifications and a sample state diagram, emphasizing synchronous reset and positive-edge triggered transitions. Students must understand the mapping between HEX0 bits and seven-segment display segments to correctly display digits.

1 Introduction 1.1 Specification
The system you design cycles through and displays the first five digits of a number
—any number you want. For example, you could use five digits from your own or
your lab partner’s student number or phone number. Your submitted code may be
stored on computers outside of Canada. If you are concerned about privacy, use a
random five digit number. The goal is that each cycle, the LCD on your DE1-SoC will
display one digit of this five digit number.
The clock input to your state machine should come from pushbutton switch KEY0 on
your DE1-SoC. Every time you press switch KEY0, another number should appear. If
the first five digits of your number is “60412”, the LED should display a “6” one the
first cycle, then “0” in the second cycle, then a “4” in the third cycle, etc. On the
sixth cycle, it should cycle back to “6” and start again. The seven segments of the
seven segment display are each controlled by each bit of HEX0[6:0]. A segment
turns on if the corresponding bit is 0 and off when that bit is 1 (this might be
opposite to what you would expect). The mapping from bits of HEX0 to segments
can be seen on the right side of Figure 1.
To add a bit of a challenge (and make the lab more fun), the user (i.e., your TA)
should be able to change the “direction” of cycling through the digits using slider
switch SW0 on your DE1-SoC. If this switch is “up” (corresponding to logic value
“1”), the system operates as described above. If this switch is “down”
(corresponding to a logic value of “0”), the system should cycle “backwards” (but
still starts with the first character). So, in the above example the order would be
“621406”.
To make things even more interesting (and fun), the user should be able to change
the slider switch during any cycle. So, for example, you might go “forwards” for 4
cycles, “backwards” for 2 cycles, and “forwards” for 4 cycles, outputting a display of
“6041404126”.
Your design should include a reset input controlled by pushbutton switch KEY1. Your
state machine should reset on the rising edge of clk if KEY1 is pressed. Note KEY0
and KEY1 output a 1 when NOT pressed and a 0 when pressed (this is probably the
opposite of what you would expect).
Figure 1 shows the overall system you will build.
2 Lab Procedure
Design a state machine in Verilog to implement the circuit as described above. A
sample state diagram might be something like the one shown in Figure 2 and
assuming you used the first five digits of your phone number and your phone
number happens to be “604-827-4116”.
The reset should be synchronous. This means that when the reset signal is asserted
(set to logic 1), the state machine is reset on the next rising edge of the clock.

Again, remember that the actual output of the KEY1 will be 0 when you press the
key and 1 when it is not pressed.
The state machine is positive-edge triggered. This means that the transition from
one state to the next occurs on the rising edge of the clock. Given KEY0 is 0 when
pressed and 1 when not pressed, you should think carefully about exactly when
your circuit will see the rising edge.
The output of the state machine is connected to the signal HEX0. You should be
able to figure out what should be driven on the signal HEX0 to display a given
number given the information in Figure 1. You will need to determine the 7-bit value
that will display the number corresponding digit you want to put on the hex display.
For example, 7’b0000010 will display a “6” because the one in bit position 1 turns off
the LED corresponding to HEX0[1]. Similarly, 7’b0011001 will display a “4” because the
ones in bit positions 0, 3 and 4 turn off the LEDs corresponding to HEX0[0], HEX0[3],
and HEX0[4]. See Figure 3. The output of your state machine should depend only on
the state it is in (and not the current input). If you end up getting a job where you
do hardware design regularly you will probably hear people talk about “Moore”
state machines, which is just a fancy name for a state machine in which the output
only depends upon the current state (and not also the current input).
Put your synthesizable code in a file called lab4_top.v. You can start with the
template version on Piazza. The code provided on Piazza uses signal names that
correspond with pin assignments in the pin assignments file, DE1_SoC.qpf, from Lab
3, which you should also use for Lab 4.
You should also create a testbench file lab4_top_tb.v that simulates inputs on the
pushbutton and slider switch to verify that your design works. Save your waveform
format in a file lab4_wave.do. You will need to show the results of your simulations to
your TA before demonstrating the design on a DE1-SoC.