System Verilog Project: VGDL Manchester Encoding and Simulation

This document details a comprehensive project on VGDL Manchester encoding, a crucial technique in digital communication. The project involves the creation of System Verilog source descriptions for key components like the 'ManchTrans' block, clock divider, pseudo-random bit sequence (PRBS) generator, and divider error modules. The solution includes VHDL code for the clock divider and PRBS generator for comparison and implementation. The project emphasizes behavioral simulations using the Vivado simulator to verify the functionality of the design, including the generation of waveforms for different modules. Furthermore, the document explores different simulation processes such as logic and timing simulations, providing insights into their applications and methodologies. The project culminates in the behavioral simulation of the 'ManchTrans' block, demonstrating the encoding and decoding of Manchester-encoded data. The document showcases the design flow, implementation, and simulation results, offering a practical guide to understanding and implementing Manchester encoding.