Create a New Quartus I Project for your Circuit

Added on - 16 Sep 2019

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Create a new Quartus II project for your circuit.Part 1Consider the circuit shown in Figure7. It uses a two-bit wide 3-to-1 multiplexer to enable the selection of threecharacters that are displayed on a 7-segment display. Using the 7-segment decoder from Part IV this circuit candisplay the characters d, E, ‘blank’ and 0, 1, or 2 depending on your DE-series board. The character codes areset according to Table3by using the switchesSW5−0, and a specific character is selected for display by settingthe switchesSW9−8.An outline of the Verilog code that represents this circuit is provided in Figure8. Note that we have used thecircuits from Parts III and IV as subcircuits in this code. You are to extend the code in Figure8so that it usesthree 7-segment displays rather than just one. You will need to use three instances of each of the subcircuits.The purpose of your circuit is to display any word on the three 7-segment displays that is composed of thecharacters in Table3, and be able to rotate this word in a circular fashion across the displays when theswitchesSW9−8are toggled. As an example, if the displayed word is dE1, then your circuit should produce theoutput patterns illustrated in Table4.Figure 7: A circuit that can select and display one of three characters.SW9−8Characters00dE101E1d101dETable 4: Rotating the word dE1 on three displays.LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY part5 ISPORT ( SW: INSTD_LOGIC_VECTOR(9 DOWNTO 0);LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6) );END part5;ARCHITECTURE Behavior OF part5 ISCOMPONENT mux_2bit_3to1PORT ( S, U, V, W: INSTD_LOGIC_VECTOR(1 DOWNTO 0);M: OUTSTD_LOGIC_VECTOR(1 DOWNTO 0));END COMPONENT;COMPONENT char_7segPORT ( C: INSTD_LOGIC_VECTOR(1 DOWNTO 0);27-segmentdecoder0001102222SW9SW8SW45SW23SW0170123456