Engineering Design: Multiplexer (MUX) Circuit Design and Analysis

This article discusses the design and analysis of a multiplexer (MUX) circuit, including design specifications, stakeholder's design brief, project schedule, planning techniques, critical path, current industry standards, evaluation tools, design techniques, modelling of design, technical solutions, and more.

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ENGINEERING DESIGN
By Name
Course
Instructor
Institution
Location
Date

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Contents
Introduction.................................................................................................................................................2
TASK 1:......................................................................................................................................................3
Design Specification................................................................................................................................3
Stakeholder’s Design Brief......................................................................................................................4
Project Schedule......................................................................................................................................6
Planning Techniques...............................................................................................................................7
Critical path:............................................................................................................................................8
Current Industry Standards......................................................................................................................8
TASK 2.....................................................................................................................................................10
Evaluation tools.....................................................................................................................................10
Design Techniques................................................................................................................................10
Modelling of Design..............................................................................................................................11
Technical Solutions...............................................................................................................................11
Task 3........................................................................................................................................................12
Engineering Design:..............................................................................................................................12
Potential Limitations:............................................................................................................................15
Finished Product Specification..............................................................................................................16
Safety and Risk Management Issues......................................................................................................16
Product effectiveness.............................................................................................................................16
TASK 4.....................................................................................................................................................17
Design Solution.....................................................................................................................................17
Communication Strategies.....................................................................................................................19
Effective Communication strategy............................................................................................................19
Justify potential improvements for the design...........................................................................................19
Conclusion.................................................................................................................................................20

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Table of figures
Figure 1: Showing the circuit diagram of 4×1 MUX...................................................................................4
Figure 2: Showing the circuit diagram of 4*1 MUX designed and tested in Multisim................................6
Figure 3: Showing the Project Schedule......................................................................................................7
Figure 4: Showing state diagram...............................................................................................................14
Figure 5: Showing 4*1 MUX designed in MULTISIM..................................................................................19
List of tables
Table 1: Showing the truth table................................................................................................................14
Table 2: Showing Boolean equations........................................................................................................15
Table 3: Showing Boolean equations........................................................................................................15
Table 4: Showing Boolean equations........................................................................................................15
Table 5: Showing Boolean equations........................................................................................................16

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Introduction
A multiplexer (MUX) is a digital electronic device which allows one or several low speed
/ digital signal at the input to be selected, transmitted and also combined at a higher speed on one
shared medium. Therefore many inputs may share one device or transmission wire like copper or
aluminium or even optic fibre. Hence MUX operates as multiple input and single output. Some
key design specification must be employed to help realize the exact required product after the
design. The design specifications given will be compared with the stakeholders´ specifications to
help design and produce a product which will operate even better than those which are already in
the market. And before the design is conducted there must be a project plan to help give the best
designs well the construction of the real/ actual prototype of the design.
MUX can be in different types depending on the input for example if the inputs are 2
then it will be known as 2 channel or 2×1. If the inputs are 4 like the one we designed it will be
known as 4 channels or simply 4×1 and it can be illustrated below;

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Figure 1: Showing the circuit diagram of 4×1 MUX
TASK 1:
Design Specification.
This MUX is designed to have 4 inputs and one output hence it helps in transmission of a large
amount of data over a small number of channels or lines. Digital MUX This MUX is designed
with several logic gates which are combined together. In this design, there are two select pins
which are realized by the use of two NOT gates. There are also 4 inputs which are realized by
the use of AND gates. These six gates are combined to two OR gates which gives one output.
All the applied logic gates give a perfect working MUX which is a combinational logical device.
The output of the MUX will give 1 (shown by the lighting of the bulb given at the output of the
MUX) only when one of the input lines is one.

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Stakeholder’s Design Brief.
Basically, the design requires the use of the combinational logic gates which help in getting one
output digital data. Broadly speaking the MUX can give output (1) when there is input in one of
the four inputs and the select pins will also be employed to help realize this.
Specification nevertheless requires that MUX should be able to give output when there is a
signal in at least one of the 4 input lines. These design necessities have been included in design
by restricting the number of logic gates employed in the design. The stakeholders have at the
same time been categorically inquired for inclusion and use of the three types of logic gates
(AND gates, NOT gates and OR gates) during the designing of the circuit. Basically, there are
some types of logic gates like the XNOR, XOR, NAD, NOR but these could not give the correct
design of the MUX. Rendering to these variables the combinational logic to drive inputs of these
logical gates has been tested to be fit to suit the requirements and the specifications of the design.
The diagram below illustrates the design of the MUX designed and tested in a MULTISIM.

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Figure 2: Showing the circuit diagram of 4*1 MUX designed and tested in Multisim
Project Schedule
Fig
ure
3:
Showing the Project Schedule
Implementation
Download design on
Hardware Test Design Sign Off
Debug Cycle
Identify points of
Failures Find cause of failure Fix Failure and Test
HDL Implementation
Design Circuit Test Circuit
Initial Phase
Circuit Implementation Plan Test Plan
Design Freeze
Design requirement Document Design Test Document
Design Specification
Carefully Read and Fathom the
Design Specification Examine Feasibility

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Planning Techniques
The technique followed for the product is based on utilizing computers for simulating the
design before the real item is made on hardware. Typically a widely utilized approach within the
industry. The most preferences of the approach are decreased time in the redesign of the product
in case of unexpected possibility issues. The design in HDL implementation stage can capture a
lot of issues that might come up in real design. The approach moreover permits designers to
make more than one design for the same circuit. Some choices make way for comparison of
diverse implementations and scrutiny of the advantages of one kind of design over the other
designs.
The later the adjustment in the design, the more expensive it is to oblige those adjustments in
design. Modelling based approach decreases this cost significantly. The issue with modelling
based approach is an incapacity to see the real item working in real circumstance. Regularly
modelling stages operate the model of the product model at much lower rates compared to what
they are anticipated to run at in real-world situation. This makes it essential to test the design not
only in demonstrating the environment but moreover in its real utilization scenario. It is actually
encouraged that the design is done in software then it is properly tested using the same software
until it works perfectly as anticipated to work1. This will help in reduces the costs that would
1 Zhang, Jingyun. 2010. Analysis and design of integrated, etched grating Dense Wavelength
Division Multiplexers. Beijing: Cornell University. https://books.google.co.ke/books?
id=C2BUAAAAYAAJ&q=design+of+MUX&dq=design+of+MUX&hl=en&sa=X&ved=0ahUKEwj4n8b
y_c3hAhXX63MBHe3DBcIQ6AEIXzAJ.
Zheng, Lizhen. 2017. High-speed Rapid-single-flux-quantum Multiplexer and Demultiplexer Design and
Testing. California: University of California, Berkeley. https://books.google.co.ke/books?
id=zq9PAQAAMAAJ&q=design+of+MUX&dq=design+of+MUX&hl=en&sa=X&ved=0ahUKEwj4n8b
y_c3hAhXX63MBHe3DBcIQ6AEIUzAH.

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have been incurred if the actual device was constructed without having the model simulated and
check the errors. The use of the model and computer simulations also help a lot in saving the
time which would have been wasted when the real product was fabricated and it had an error. As
this will imply that another product will be constructed again and again until the one which has
the required specifications is made. In most cases, this cannot be realized due to errors of a
human. Therefore it is very important to simulate before constructing the real product.
Critical path:
For every serious project done like this, there are several small activities which are done to help
realize the overall objective of designing the overall product with the required specifications.
Each activity has its own goals and its requirements for inputs. Sometimes the output of one
activity is input to the other activity. When the previous task is not completed on time, it affects
the starting time of the following activity. Depending upon delays in activity completion, the
task might become the bottleneck for the project to progress further. The Critical Path Method is
defined in the Project Management Body of Knowledge (PMBOK) as follows: “The Critical
Path”
The method is the sequence of scheduled activities that determines the duration of the
project." Any project has a set of activities that are critical and some are non –critical.
This too may change during the execution of the project that a few exercises that were at
first non-critical have currently become critical in the sense that their completion is holding up

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the progress of the project and must be performed urgently in case the project is to be completed
effectively. Basic path recognizes the chain of assignments that must be completed precisely on
time to avoid project from getting postponed.
Current Industry Standards
The present design has the specification as given in the stakeholder's necessity document.
There are several variations of the same circuit present in the market which permits from extra
functionality to the design at added cost and size of the designed product2. Future versions of the
product can be expected to have that some other functionality like parallel load, reset and hold
functions when there is a need. Actually, these extra functionalities will enable the product to
operate better than the current products which are in the market. These functionalities will even
attract more customers to buy them over the current products already in the market.
2 Sachdev, Manoj. 2018. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled
Technologies: Process-Aware SRAM Design and Test. Sydney: Springer Science & Business
Media. https://books.google.co.ke/books?
id=OXigu7wLa34C&dq=design+of+MUX&source=gbs_navlinks_s.
Vahid, Frank. 2010. Digital Design with RTL Design, Verilog and VHDL. Hull: John Wiley & Sons.
https://books.google.co.ke/books?id=-
YayRpmjc20C&dq=design+of+MUX&source=gbs_navlinks_s.

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TASK 2
Evaluation tools
As per now there a lot of software which can be employed to make the design of this circuit, this
software can be applied for both large scale production and small scale production. Depending
on the user specifications any of the platforms can be employed. The platforms considered for
the current product development included Multisim from Nation Instruments, Orcad Pspice from
Cadence and open source software like Logisim and Logically. But for this project, Multisim
software was used for the development and testing of the device as it is a standard and reliable
software. This is because it is very easy to use Multisim in designing this circuit diagram and test
for the operation of the 4×1 MUX. The circuit diagram obtained from Multisim is can be
illustrated in figure 1 above.
Design Techniques
Standard design strategies are followed when designing the system utilizing digital
components present in the market with demonstrated functionality and determination. Once all
states and their transitions to another state are recognized, the diagram is mapped to a truth table
that shows the same data in the digital domain. The concluded truth table is then diminished to
useful Boolean equations in minimized form. Once the required equation is derived, the circuit is
designed in a simulation environment and tried thoroughly for all functional specifications.
When there is an error during testing then the error can be debugged (corrected) until we have
the final circuit diagram which operates as required by the designer.

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Modelling of Design
The design solution created is modelled and tested in Multisim software utilizing
standard library components which are in place tab of the software. The inputs expected for the
circuit are emulated utilizing available gadgets3. All possible input conditions for changing time
lengths are tested on the circuit. Once all conditions are checked and confirmed to be in the state
as required, the circuit is considered mature for another stage is implementation. The simulation
included connecting logic gates in the circuit at the posedge of it. The inputs which are AND
gates are connected to their own combination circuits utilizing an arrangement of OR doors. The
control flag up/down is additionally driven as a portion of the testbench.
Technical Solutions
Currently, there are a lot of choices which can be employed to realize the functional
circuit using high-level components like ROM and MUX for the combinational part of the
design. Nevertheless, individual gate based approach was used as it was most effective in terms
of the logic gate and minimized area and optimized speed. Cost of design using gates was also
less compared to high-level design components. So a gate based design was deduced and
implemented. And for every design of the large scale production cost of the design must be
3 Bertacco, Valeria. 2018. Functional Design Errors in Digital Circuits: Diagnosis Correction and
Repair. London: Springer Science & Business Media. https://books.google.co.ke/books?
id=S8fUrOUOx0AC&dq=design+of+MUX&source=gbs_navlinks_s.
Berube, Richard. 2014. Computer Simulated Experiments for Digital Electronics Using Electronics
Workbench Multisim. Stoke: Prentice Hall PTR. https://books.google.co.ke/books?id=-
6vWAAAAMAAJ&dq=Digital+electronic+design+in+MULTISIM,&hl=en&sa=X&ved=0ahUKEwjL_O
C3g87hAhWCk4sKHd2nA74Q6AEINTAC.

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checked and in most cases, there should be attempts to reduces it as much as possible to help
realize a lot of profit.
Task 3
Engineering Design:
A MUX is a circuit which gives one output from several inputs, these can be 2, 4 depending on
the select pins used in the circuit diagram4. For two select pins, there will be four input pins
while when there is one select pin there will be two input pins. But still, these two different types
of MUX will operate the same way. When there is a signal at the output the circuit gives an
indication by the use of the blowing bulb in the MULTISIM. And this can be illustrated the
figure 2 above. The Boolean expression for the 4*1 MUX is given by the following equation;
The function of MUX In data communication, it´s is used to increases the efficiency of the
system through permitting the transmission of video, audio and data signals on the similar carrier
line. Voice communication schemes, like the telephone system.
4 Rafiquzzaman, Mosses. 2014. Fundamentals of Digital Logic and Microcomputer Design.
Chicago: John Wiley & Sons. https://books.google.co.ke/books?
id=1QZEawDm9uAC&dq=design+of+MUX&source=gbs_navlinks_s.
Sachdev, Manoj. 2018. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies:
Process-Aware SRAM Design and Test. Sydney: Springer Science & Business Media.
https://books.google.co.ke/books?
id=OXigu7wLa34C&dq=design+of+MUX&source=gbs_navlinks_s.

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STATE DIAGRAM:
Figure 4: Showing state diagram
TRUTH TABLE:

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Table 1: Showing the truth table
Input 1
(i0)
Input 2
(i1)
Input 3(i2) Input 4(i3) Select
Line(S1,S0
)
Output
(o0)
0 X X X 00 0
1 X X X 00 1
X 0 X X 01 0
X 1 X X 01 1
X X 0 X 10 0
X X 1 X 10 1
X X X 0 11 0
X x x 1 11 1
Optimized Boolean Equation
k- Map representation for o0 is
CASE I1=X; I2=X; I3=X
Table 2: Showing Boolean equations
S1’S0’ S1’S0 S1S0 S1S0’
I0’ 0 0 0 0
I0 1
O0 = S1’S0’I0
CASE I0=X; I2=X; I3=X

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Table 3: Showing Boolean equations
S1’S0’ S1’S0 S1S0 S1S0’
I1’ 0 0 0 0
I1 1
O0 = S1’S0’I1
CASE I0=X; I1=X; I3=X
Table 4: Showing Boolean equations
S1’S0’ S1’S0 S1S0 S1S0’
I2’ 0 0 0 0
I2 1
O0 = S1’S0’I2
CASE I0=X; I1=X; I2=X
Table 5: Showing Boolean equations
S1’S0’ S1’S0 S1S0 S1S0’
I3’ 0 0 0 0
I3 1
O0 = S1’S0’I3

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Combining the above equations in the form of an SOP Boolean equation, o0 can be represented
as:
O0 = S1’S0’I0 + S1’S0I1 +S1S0’I2 + S1S0I3
Potential Limitations:
The design given here is to give one output from 4 different input controlled by 2 select
pins, the great limitation for this design is the correct use of the correct types and correct number
logic which will give the correct results. Another limitation of the MUX is the failure of
distinctive signed and unsigned combinational logic gates. In case of a signed logic gate, the
given design will need to be modified to suit the specifications required by the designer.
Finished Product Specification
The 4*1 MUX is a combinational digital device which was designed from the adopted
design specifications. The use of the different logic gates of any type was employed to give the
determined design specification. The use of OR, NOT and AND gates was employed for the
design of this circuit which gave better operational results when it was simulated in the Multisim
software.
Safety and Risk Management Issues
Compliance of the item designed will depend upon chosen technology like TTL or
CMOS and other logic families. The Circuit will require a consistent source of the power supply
with few mA of current5. It is anticipated the circuit is appropriately grounded and all its metal
5 Langholz, Gideon. 2018. Foundations of Digital Logic Design. Florida: World Scientific.
https://books.google.co.ke/books?
id=4sX9fTGRo7QC&dq=design+of+MUX&source=gbs_navlinks_s.

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wires are typified sufficiently to prevent any hurt due to accidental touching of the board during
operation. In case of disposing of the item after use or harm, make beyond any doubt the board is
kept with the capable reusing unit as parts may contain certain harmful materials. Board too
contains sharp edges components that must be dealt with carefully in times of replacement and
be kept out of reach of children.
Product effectiveness
Through testing of the gadget has been carried out under simulation and under physical
testing conditions for useful correctness and meeting operational necessities. The board has been
tested for rated voltages and current levels as given by person component producers. The product
hence met all the required specifications as stated above and the product is hence declared good
and sit for use and will be sold to the market for the purchase of the interested individuals at a
reasonable price.
TASK 4
Design Solution
The diagram below shows the operation of the simulation of the final designed product
of the MUX. The design has four different input linesI0, I1, I2 and I3 together with the two
select lines S0 and S. These two select lines S0 and S1 are connected to the NOT gate to negate
them for signals taken to the first two AND gates and the non-negated select lines signals taken
Mishra, Khusbou. 2015. Low Power High Speed CMOS Multiplexer Design. Mancheter: Nova Science
Publishers, Incorporated. https://books.google.co.ke/books?
id=w1DKrQEACAAJ&dq=design+of+MUX&hl=en&sa=X&ved=0ahUKEwj4n8by_c3hAhXX63MBHe
3DBcIQ6AEITTAG.

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to the last two AND gates. Signals from the first two AND gates are taken to the first OR gate
and the same is done to the signals of the last OR gate. The two signal from each OR gate is
then taken to the OR gate of the final design which gives the output.

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Figure 5: Showing 4*1 MUX designed in MULTISIM
Communication Strategies
The communication strategies employed in this circuit diagram is between the logic gates
which gets the signals from the input lines I0 to I3 and also the select lines. The signals will then
be transferred to the 4 AND gates than to the first 2 OR gate and last the one final OR gate where
the output is finally given. The communication strategy here is that simple, just the transfer of
signal from one logic gate to the other. When the stakeholders understand the operation and the
communication of signal in the designed MUX it becomes easier for them too to explain and sell
the product since they can fully explain the flow of the signal in the designed electronics.
Effective Communication strategy
The communication strategy for the design of 4 *1 MUX is very vital for this design.
This is because it illustrates smart marketing plans for the newly produced design. It takes its
cues from the marketing strategy, which, in turn, takes its course from the business strategy. In
other words, the communication strategy will enable the producers to perfectly market the
produced device. By this, the producers will give sufficient information about the item before
they buy it.
Justify potential improvements for the design.
To help give a good frequency in telecommunication, during the design of the MUX
several input lines, as well as the select pins, can be used. This improvement will hence make
the circuit to give quality frequencies which are desired in the design. For example, about 3
select pins can be employed and this will give 8 inputs pins which will be given to the logic gates
and the data will be transferred until it reaches the output.

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Conclusion
The design of 4*1 MUX was perfectly done and the desired specifications were met after
the design. These specifications were exactly the same to those of the stakeholder making our
design to meet the required quality in the market. The designed MUX can be employed in giving
very smooth frequency in the sector of telecommunication. The design was tested in a
MULTISIM software before the actual device was made. As seen above this has several
advantages over giving the final design without simulation. For example, this will help to save
on cost, time among others.
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6vWAAAAMAAJ&dq=Digital+electronic+design+in+MULTISIM,&hl=en&sa=X&ved=0ahUKEwjL_O
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Wiley & Sons. https://books.google.co.ke/books?
id=1QZEawDm9uAC&dq=design+of+MUX&source=gbs_navlinks_s.
Sachdev, Manoj. 2018. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies:
Process-Aware SRAM Design and Test. Sydney: Springer Science & Business Media.
https://books.google.co.ke/books?
id=OXigu7wLa34C&dq=design+of+MUX&source=gbs_navlinks_s.
Vahid, Frank. 2010. Digital Design with RTL Design, Verilog and VHDL. Hull: John Wiley & Sons.
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YayRpmjc20C&dq=design+of+MUX&source=gbs_navlinks_s.
Zhang, Jingyun. 2010. Analysis and design of integrated, etched grating Dense Wavelength Division
Multiplexers. Beijing: Cornell University. https://books.google.co.ke/books?
id=C2BUAAAAYAAJ&q=design+of+MUX&dq=design+of+MUX&hl=en&sa=X&ved=0ahUKEwj4n8b
y_c3hAhXX63MBHe3DBcIQ6AEIXzAJ.
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Testing. California: University of California, Berkeley. https://books.google.co.ke/books?
id=zq9PAQAAMAAJ&q=design+of+MUX&dq=design+of+MUX&hl=en&sa=X&ved=0ahUKEwj4n8b
y_c3hAhXX63MBHe3DBcIQ6AEIUzAH.