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NG2S902 - Analogue and Digital Electronics

   

Added on  2019-09-30

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FACULTY OF COMPUTING,ENGINEERING and SCIENCEFinal mark awarded:_____Assessment Cover Sheet and Feedback Form 2015/16Module Code:NG2S902Module Title:Analogue and Digital Electronics2Module Lecturer:Glyn RobinsAssessment Title and Tasks: Sequential Logic Design. (ReferralAssessment No. e.g. 2No. of pages submitted in total including this page:Completed by studentWord Count of submission(if applicable):Completed by studentDate Set:2nd June 2016Submission Date: 3rd August 2016Return Date:Part A: Record of Submission (to be completed by Student)Extenuating CircumstancesIf there are any exceptional circumstances that may have affected your ability to undertake or submit this assignment, make sure you contact the Advice Centre on your campus prior to your submission deadline.Fit to sit policy:The University operates a fit to sit policy whereby you, in submitting or presenting yourself for an assessment, are declaring that you are fit to sit the assessment. You cannot subsequently claim that your performance in this assessment was affected by extenuating factors. Plagiarism and Unfair Practice Declaration:By submitting this assessment, you declare that it is your own work and that the sourcesof information and material you have used (including the internet) have been fully identified and properly acknowledged as required1. Additionally, the work presented hasnot been submitted for any other assessment. You also understand that the Faculty reserves the right to investigate allegations of plagiarism or unfair practice which, if proven, could result in a fail in this assessment and may affect your progress.Details of Submission:Note that all work handed in after the submission date and within 5 working days will be capped at 40%2. No marks will be awarded if the assessment is submitted after the late submission date unless extenuating circumstances are applied for and accepted (AdviceCentre to be consulted).Work should be submitted as detailed in your student handbook. You are responsible forchecking the method of submission.You are required to acknowledge thatyou have read the above statements by writing your student number (s) inthe box:Student Number(s):1University Academic Integrity Regulations2 Information on exclusions to this rule is available from Campus Advice Shops

IT IS YOUR RESPONSIBILITY TO KEEP A RECORD OF ALL WORKSUBMITTEDPart B: Marking and Assessment(to be completed by Module Lecturer)This assignment will be marked out of 100%This assignment contributes to 15% of the total module marks.This assignment is bonded. Assessment Task: Scenario:You are to design synchronous and asynchronous circuits that will allow the following requirements to be met. Tasks:1.Packet number checkingA synchronous sequential machine is to have a single input line and a single output line. The circuit is to receive messages of 4-bit words coded in binary (least significant bit first). The purpose of the circuit is to detect whether the number coming in is a prime number (divisible by only itself and 1). Thus, the output is to become 1 whenever a 4-bit word does represent a valid prime number. At the end of each word the machine is to return to the reset startingstate.Steps:1)Draw a State Diagram (Mealy) and check for redundancies2)Then assign binary State Identifiers.3)Make a Next State Truth Table (NSTT)4) Select a bistable type 5)Determine expressions for the bistable inputs6)Determine expressions for the outputs2. Monitoring SystemA monitoring system sends a fixed duration positive going pulses to a device to ensure that it is operating correctly. The device will respond by lowering itsnormally high line as soon as it receives the pulse then raising the line again within the 1s if working correctly. If the device line doesn’t respond correctly by not raising the line or raising it then lowering it within the pulse period an alarm must occur. No response is not an alarm condition.1)Carry out a design for the asynchronous system that will realise the requirements up to the point where internal conditions are designated to the lines in the merged table.2)Explain what the designer would have to do to ensure the system was hazard free and the output was as short as possible.Learning Outcomes to be assessed (as specified in the validated module descriptor http://icis.glam.ac.uk):1. Critically evaluate the technologies and design techniques used in electronic circuit and system design.2. Design electronic circuits and systems using appropriate modern technologies and techniques to meet technical and commercial specificationsGrading Criteria49% - 40%A Pass grade is recommended for the achievement of the learning outcomes 59% - 50%In order to achieve a percentage in this range the student must:

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