ITC544 - Data Representation & Digital Logic Assignment

ITC544
Computer Organisation and Architecture
Assignment 1
Data Representation & Digital Logic
Student Name:
Student ID:

Contents
Question 1........................................................................................................................................3
Question 2........................................................................................................................................6
Question 3........................................................................................................................................9
Lists of Figures
Figure 1: Logical diagram of 2 (a)...................................................................................................6
Figure 2: Logical diagram of 2 (b)..................................................................................................8
Figure 3: Logical diagram of 3........................................................................................................9

Question 1
(a) 0x2ED1 to Binary
The given numbers are converting in the binary type which can be done by using the
mapping method. For that purpose, the representation of a hexadecimal number into the
binary is providing below:
2 – 0010
E - 1110
D - 1101
1 – 0001
To get the final result of this conversion, the value will combine from the top to bottom
which is as follow 00101110110100012
(b) −29.6610 to Binary
The given numbers are splitting into two parts which are 29 and .66 then, division rule is
utilizing for the first part. So, - 29 will convert into binary format.
For first part (29)
Divisor Value of Dividend Value of Remainder
2 29 1
2 14 0
2 7 1
2 3 1
2 1 1
0
To get the result of this conversion, the value will combine from the bottom to up which is as
follow 111012 for 29
Conversion for second part so, 0.66 will convert into binary format.
Numbers Multiplied with Multiplex’s result Value of Remainder
0.66 2 1.32 1
0.32 2 0.64 0
0.64 2 1.28 1
0.28 2 0.56 0

0.56 2 1.12 1
0.12 2 0.24 0
0.24 2 0.48 0
0.48 2 0.96 0
0.96 2 1.92 1
0.92 2 1.84 1
0.84 2 1.68 1
0.68 2 1.36 1
0.36 2 0.72 0
0.72 2 1.44 1
0.44 2 0.88 0
0.88 2 1.76 1
0.76 2 1.52 1
0.52 2 1.04 1
To get the result of this conversion, the value will combine from the top to bottom which is
as follow 1010100011110101112 for 0.66. The final result of this conversion is as follow
11101. 1010100011110101112
(c) 1001111001102 to Hexadecimal
The given numbers are converting in the hexadecimal type which can be done by using the
mapping method. For that purpose, the representation of a binary number into hexadecimal is
providing below:
1001 – 9
1110 – E
0110 – 6
To get the final result of this conversion, the value will combine from the top to bottom
which is as follow 9E616
(d) 11101110 (8-bit 2’s complement representation) to decimal
This question is solving into the numbers of steps which are given below:
1. The given number LSB bit is 1 so the conversion of this number will negative.
2. Taking the 1’s complement of given number 11101110 which can be done by changing 0
to 1 or 1 to 0 that is providing below:

0 0 0 1 0 0 0 1 (1’s complement)
3. Now, add 1 with the value of 1’s complement
0 0 0 1 0 0 1 0 (2’s complement)
4. Then, value of 2’s complement is converting into decimal type of number which can be
done via multiplying 2x here x is representing 7 to 0.
0*27 + 0*26 + 0*25 + 1*24 + 0*23 + 0*22 + 1*21 + 0*20
= 0*128 + 0*64 + 0*32+1*16 + 0*8 + 0*4 + 1*2 + 0*1
= 0 + 0 + 0 +16 + 0 + 0 + 2 + 0 = - 18.
(e) 1 01111110 11000000000000000000000
Stage 1:
The given expression is splitting into three portions that are as follows:
1 – Sign
01111110 - Exponent
11000000000000000000000 – Fraction
Stage 2:
The bit of sign portion is 1 therefore, conversion will negative.
Stage 3:
Then, the bits of exponent will convert in the decimal format which is as follows
0*27 + 1*26 + 1*25 + 1*24 + 1*23 + 1*22 + 1*21 + 0*20
= 0*128 + 1*64 + 1*32+1*16 + 1*8 + 1*4 + 1*2 + 0*1
= 0 + 64 + 32 +16 + 8 + 4 + 2 + 0 = 126
Step 4:
The value of exponent 126 value will subtract the bias value that is 127 for single type of
precision number therefore, the 2’s power will – 1.
Step 5:
Then, the bits of fraction will convert in the decimal format which is as follows
1*2-1 + 1*2-2 = 0.75
Step 6:
Then, the final value of this conversion will – 1.75 * 2-1 = -0.875 = - 8.75 * 10-1

Question 2
(a) There are numbers of universal gates such as NAND and NOR gates. These types of
universal gates are using to create a different kind of combinational circuit. These two
universal gates are using via different kinds of users.
Here inverter is creating with the help of NAND gate and this inverter will convert zero
into one and one into zero which is representing with the help of truth table. This truth
table is consisting of output and input ports. The design circuit is also representing below:
Figure 1: Logical diagram of 2 (a)
A truth table of inverter:
Input Output
A B
0 1
1 0
The logical type of equation is providing as follow which is B = ͞ A.
(b) Here, 3 components of course are providing below:
Quiz = Q, Assignment = A, and Journal = J
The numbers of the students will pass in the course if they will pass two or more
components of the courses which are denoted via P. For that purpose, the truth table can
create as follow that is providing below:
Truth table:
Inputs Output
Q A J P
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

In this table, 0 is representing the fail and 1 is representing the pass for the numbers of
courses.
Circuit designing of this table:
The circuit design can form by using the truth table and equation for this circuit design
can extract by using the Karnaugh map.
A, J
00 01 11 10
0
1 Q
The final equation of this table is creating with the help of this Karnaugh map that is
providing as follow:
P = AJ + QJ + QA
Logical diagram:
Figure 2: Logical diagram of 2 (b)
0 0 1 0
0 1 1 1

Question 3
Figure 3: Logical diagram of 3
The truth table is generating by using this given logical diagram which is containing the three
inputs such as X, Y, Z and one output such as F. The 0 and 1 is using at the 3 inputs and output is
getting at F point.
Truth table:
The logical equation is extracting by using the Karnaugh map that is representing as follow:
Y, Z
00 01 11 10
0
1 X
Inputs Output
X Y Z P
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
0 0 1 1
1 1 0 0

The final equation of this table is creating with the help of this Karnaugh map that is
providing as follow:
F = ͞ XY + ͞ YX