Understanding Operating Systems: Memory Management and TLB in a Nutshell

In this question answers we will discuss about operating system and below are the summaries point:- The operating system manages the mapping of physical memory and virtual memory addresses, utilizing paging or swapping techniques. During the replacement of a TLB entry, it needs to be written back to physical memory, and a backing store is used for page fault management. The TLB contains mapped virtual page numbers, including various bits such as present, referenced, protection, and dirty bits, and it plays a crucial role in memory access efficiency.

Running head: OPERATING SYSTEM
Operating System
Name of the Student
Name of the University
Author’s Note

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Answer to Question 1:
The pages in physical memory is owned by the systems. The pages are contiguous
blocks of fixed length and can be described as a single entry in page table. The pages are
mapped with the operating system and it can be transferred between the hard drive and
known as paging or swapping. For the extraction of the page number the logical address is
used and TLB is consulted for obtaining the frame number. In case the TLB is missed the
page table is consulted and frame number is fetched.
The system is responsible for mapping the physical memory with the virtual memory
addresses. It also automatically manages the space of physical memory transparently and thus
the programmer is needed to know the size of physical memory for running any program. The
physical memory acts as a cache for the pages stored on the disk and mapping with any
physical frame.
Answer to Question 2:
During replacement of an entry in the TLB there is need to write it back to the
physical memory. This is can be described form the demand paging where a backing store is
used for the management of page fault. For storing the frame the page table and TLB are
updated and the access of the page is resolved either by page table or the TLB. The backing
store file is needed to be treated as random access file such that certain position of the file can
be seek for reading.
Answer to Question 3:
TLB consists of mapped virtual page number for the physical page number and
includes the present bit, referenced bits, protection, dirty bits and process ID. It also contains

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98% of the pages that are accessed and the size ranges from 64 to 128 entries. Smaller TLB is
fully associative and page fault and TLB miss is also different from each other.
For the simulation the program is written for reding 1001 addresses ranging from 0 to
65535 and the logical address is translated into physical addresses. The contents of the signed
bytes are determined and outputs the translated logical addresses read from the
addresses23.txt file, physical address of the corresponding logical address and signed byte
value stored for the translated physical address.
while((read = getline(&line, &len, pFile)) != -1){
int offset = atoi(line) & 255;
int page = atoi(line) & 65280;
int page_table_number = page >> 8;
int tlb_hit = 0;
for(int i = 0; i < TLB_SIZE; i++){
if(tlb[i][0] == page_table_number){
tlb_hit = 1;
printf("TLB HIT\n");
break;
}
}
if(v_memory[page_table_number][0] < 0 && !tlb_hit){
pageFaultCount++;

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srand(time(NULL));
int r = rand();
int largest = 0;
int evct = 0;
for(int i = 0; i < V_SIZE; i++){
if(v_memory[i][1] > largest){
largest = v_memory[i][1];
evct = i;
}
}
int tlb_replacement = r % 15;
tlb[tlb_replacement][0] = page_table_number;
tlb[tlb_replacement][1] = v_memory[evct][0];
v_memory[page_table_number][0] = v_memory[evct][0];
v_memory[page_table_number][1] = 0;
v_memory[evct][0] = -1;
v_memory[evct][1] = 0;
}
A statistics is generated after completing the program listing the page fault rate and
the TLB hit rate.

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The following is the output obtained after executing the program and it lists the virtual
address read from the provided txt file and the physical address of the corresponding logical
address.

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Bibliography
Ausavarungnirun, R., Landgraf, J., Miller, V., Ghose, S., Gandhi, J., Rossbach, C. J., &
Mutlu, O. (2017, October). Mosaic: a GPU memory manager with application-
transparent support for multiple page sizes. In Proceedings of the 50th Annual
IEEE/ACM International Symposium on Microarchitecture (pp. 136-150). ACM.
Yıldırım, A. A., Watson, D., Tarboton, D., & Wallace, R. M. (2015). A virtual tile approach
to raster-based calculations of large digital elevation models in a shared-memory
system. Computers & geosciences, 82, 78-88.