Data Representation and Digital Logic

The assignment is about data representation and digital logic. It covers the IEEE-754 single precision format, where a decimal number is represented as sign bit (0), exponent (8 bits), and mantissa (23 bits). The binary representation of numbers is also discussed. Additionally, the assignment explains how to represent the status of the CSU main entrance gate using Boolean expressions and logic gates. Finally, it provides a proof of a given statement X'Y + XYZ' + Y' + XZ(YY') = 1 using various laws of digital logic.

Assignment 1: Data Representation and Digital Logic
ITC544
Name: ID:

1.
a. 0 01111110 10100000000000000000000
In IEEE-754 single precision format, starting from the left, first bit denotes the sign of
the decimal number (positive or negative), next 8 bits represents the exponent of the
number and remaining bits represents the mantissa.
Following the standards:
Here, first bit (sign bit) is 0, therefore, we can say that the number is positive.
Next 8 bits are 01111110, therefore, each bit is multiplied with a power of 2 and is
then added together.
01111110 --- 0*27 + 1*26 + 1*25 + 1*24 + 1*23 + 1*22 + 1*21 + 0*20
= 126
For the exponent, 127 is subtracted from the result.
126 – 127
= -1
Exponent is -1
Now, next bits are 10100000000000000000000, in this last 20bits are 0 which will
have no effect on the mantissa as it will result to 0. Therefore,
1.101 is considered.
Multiplying with the exponent
1.101 * 10-1
= 0.1101
For the decimal number, the bits are multiplied with the negative power of 2 at the
right side of decimal point and positive power of 2 at the left side.
0.1101 --- 0*20 + 1*2-1 + 1*2-2 + 0*2-3 + 1*2-4
= 0.8125
b. “word” of 5 bits is numbers which can be represented in maximum 5bits. Therefore,
in general, these numbers start from 00000 (all 0’s) and end at 11111 (all 1’s). But for
different magnitudes, they vary.
i. Binary --- 01111 – 11111
Decimal --- -15 – 15
ii. Binary --- 10000 – 01111
Decimal --- -16 – 15
iii. Binary --- 10001 – 01111
Decimal --- -17 – 15
2.
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a. To activate the CSU main entrance gate, at some specific timings and also close it
accordingly, we need to keep a track of the time. The time calculation cannot be
represented using the basic logic gates, and hence, we can assume an input A, which
gives 1 when the time is either 9.00 – 12.00 or 13.00 – 16.00 (assuming a 24-hour
clock). For all other times, it gives 0.
Also, we have assumed, there is a switch which manages the gate denoted by B.
Therefore, the status of the CSU main entrance gate, C, is represented by the
following Boolean expression:
C = A.B
Logic Gate diagram:
Minimization:
For minimization, as this is really a simple circuit diagram with 2 inputs, 1 output and
only 1 logic gate, therefore, no minimisation is required.
But, if we assume that the switch is always on then the status of CSU main entrance
gate will be dependent only on the time, which can then be represented as
C = A
b. To Prove:
X’Y + XYZ’ + Y’ + XZ (Y+Y’) = 1
Let us consider the LHS
X’Y + XYZ’ + Y’ + XZ (Y+Y’)
X’Y + XYZ’ + Y’ + XZ.1 → Inverse law
X’Y + XYZ’ + Y’ + XZ → Identity law
Y (X’ + XZ’) + Y’ + XZ → Inverse Distributive law
Y (X’ + X) (X’ + Z’) + Y’ + XZ → Distributive law
Y.1 (X’ + Z’) + Y’ + XZ → Inverse law
Y (X’ + Z’) + Y’ + XZ → Identity law
X’Y + YZ’ + Y’ + XZ → Distributive law
X’Y + (Y + Y’) (Z’ + Y’) + XZ → Distributive law
X’Y + 1. (Z’ + Y’) + XZ → Inverse law
X’Y + Z’ + Y’ + XZ → Identity law
X’Y + Y’ + Z’ + XZ → Associative law
(X’ + Y’) (Y + Y’) + (Z’ + X) (Z’ + X) → Distributive law
(X’ + Y’).1 + (Z’ + X).1 → Inverse law
X’ + Y’ + Z’ + X → Identity law
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X’ + X + Y’ + Z’ → Associative law
1 + Y’ + Z’ → Inverse law
1 → Null law
Identities
Inverse law A + A’ = 1
Identity law A.1 = A
Distributive law A + BC = (A +B) (A + C)
Inverse Distributive law AB + AC = A (B + C)
Associative law A + B + C = A + C + B
Null law 1 + A = 1
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