Computer Organization and Architecture

The assignment content is about computer organization and architecture, specifically about data representation and digital logic. It includes a question that requires the representation of a floating-point number in IEEE-754 single precision format using binary digits and the construction of a logic diagram for a circuit that activates a main entrance door during specific time periods.

Running head: COMPUTER ORGANIZATION AND ARCHITECTURE
Student
STUDENT ID:11637042 COURSE ID: ITC 544
Data Representation & Digital Logic
Computer Org & Architecture

1
COMPUTER ORGANIZATION AND ARCHITECTURE
Q1. A Computer uses IEEE-754 single precision format to represent floating
points. What value (in decimal) the computer represents if the floating point is
represented using the following binary digits: 0 01111110 10100000000000000000000
Answer:
A) Single precision in IEEE 754 format is 0 01111110
10100000000000000000000
 S=0 thus it is a positive number
 01111110 =126
 E = 126-127=-1d
 =1.10100000000000000000000 x 2^-1
 = 0.110100000000000000000000 x 2^-1 x 2 ^1
 =0.110100000000000000000000
 =0.5+0.25+0.0625
 =0.8125
 The decimal value of the binary number is 8.125 * 10^-1
 s
B)
 Let the 5 bit word be 00110

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COMPUTER ORGANIZATION AND ARCHITECTURE
a) Its signed magnitude = -6
b) One’s Complement = 11001
c) Two’s Complement = 11010
Q2: Write a Boolean function and construct a logic diagram of a circuit which
use of basic logic gates to activate CSU main entrance door during 9:00 am to
12:00 pm and after lunch time during 1:00 pm - 4:00 pm. You need to use 24
hour clock timing when designing this circuit.
Answer:
A)
The clock is represented in the following table:
Time
Progress
The Clock Pulse Decimal Notation Representation
A B C D E
1
HIGH 1
0 0 0 0 1
2 0 0 0 1 0
3 0 0 0 1 1
4 0 0 1 0 0
5 0 0 1 0 1
6 0 0 1 1 0
7 0 0 1 1 1
8 0 1 0 0 0

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COMPUTER ORGANIZATION AND ARCHITECTURE
9 0 1 0 0 1
10 0 1 0 1 0
11 0 1 0 1 1
12 0 1 1 0 0
13
LOW 0
0 1 1 0 1
14 0 1 1 1 0
15 0 1 1 1 1
16 1 0 0 0 0
17 1 0 0 0 1
18 1 0 0 1 0
19 1 0 0 1 1
20 1 0 1 0 0
21 1 0 1 0 1
22 1 0 1 1 0
23 1 0 1 1 1
24 1 1 0 0 0
 This is the logic which is used in the preparation of the diagram:
 A'BC'D'EP+A'BC'DE'P+A'BC'DEP+A'BCD'E'P=Q (For clock= High (1))
 A'BCD'EP’+A'BCDE'P’+A'BCDEP’+AB'C'D'E'=R (For clock= Low (0))

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COMPUTER ORGANIZATION AND ARCHITECTURE
B)
X’Y+XYZ’+Y’+XZ (Y+Y’)

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COMPUTER ORGANIZATION AND ARCHITECTURE
 = X’Y+XYZ’+Y’+XZY+XZY’
 = X’Y+XY (Z+Z’) + Y’+XZY’
 =X’Y+XY+Y’+XZY’
 =Y+Y’+XZY’
 =1+XZY’
 =1
 Hence Proved.