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Running head: BOOLEAN ALGEBRABoolean algebraName of the studentName of the UniversityStudent IdSubject code (ITC544)Assignment 1: Data representation and digital logicAuthor note

Page1of8BOOLEAN ALGEBRAAnswer 1:a)Single precision IEEE 754 format- 0 01111110 10100000000000000000000In this section, the first MSB (most significant bit) is the sign, the middle portion is theexponent and the last portion is the mantissa.Decimal conversion- 8.125 * 10^-1b)5-bit word- 0 1010Signed magnitude- +10 (Most significant bit-0 [positive] rest 4 bits are magnitude)One’s complement- 10101 (all the 0’s are replaced by 1 and vice-versa)Two’s complement- 10110 (1 is added to the one’s complement)Answer 2:a)This section will represent the hours of the clock in 5-bit binary form.MagnitudeBinaryClock pulse (p)1ABCDEHigh (+1)00001200010300011400100500101600110700111

Page2of8BOOLEAN ALGEBRA8010009010011001010110101112011001301101Low (0)14011101501111161000017100011810010191001120101002110101221011023101112411000The timing diagram will supposedly use a 12-hour clock period. For 1-12 time on theclock, the pulse will give +one value. For 13-24, the pulse will give zero value. To address therequirements, the 12 am in the clock is considered as one, which will continue until the pulsereaches 24. The door will open for 9 am (9) to 12 pm (12) and 1 pm (13) to 4 pm (16). Inaddition, the binary bits will be represented by A B C D E to represent the required bits in thelogic diagram. The circuit will be made by the use of basic logic gates.The logic diagram is:A'BC'D'EP+A'BC'DE'P+A'BC'DEP+A'BCD'E'P=Q (For clock= +1)A'BCD'EP’+A'BCDE'P’+A'BCDEP’+AB'C'D'E'=R (For clock=0)

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