Computer Systems Architecture
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This assignment covers topics like data representation, functions of computer system components, principles of processor operations, and more. It explains concepts such as Von Neumann Architecture, memory types, CPU components, polling, interrupts, RISC vs. CISC chips, and the fetch-execute cycle.
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Contents
Introduction......................................................................................................................................4
LO1 Understand how data can be represented within computer systems.......................................5
P1. Explain using examples how numeric and alphanumeric data can be coded within a
computer system..........................................................................................................................5
P2. Explain using examples how different types of data can be converted and stored in
computer system..........................................................................................................................7
P3. Convert numeric data between different number systems including floating point..............9
LO2 Understand the functions of computer system components..................................................18
P5. Illustrate the key computer system components and how they interact..............................18
P6. Explain the different types of memory that can be attached to a processor........................21
P7. Explain how polling and interrupts are used to allow communication between processor
and peripherals...........................................................................................................................24
LO3 Understand the principles of processor operations................................................................25
P8. Compare Reduced Instruction Set Computer (RISC) chips and Complex Instruction Set
Computer (CISC) chips .............................................................................................................26
P9. Illustrate the use of the different processor registers in the fetch-execute cycle.................29
Conclusion.....................................................................................................................................32
References......................................................................................................................................33
1
Introduction......................................................................................................................................4
LO1 Understand how data can be represented within computer systems.......................................5
P1. Explain using examples how numeric and alphanumeric data can be coded within a
computer system..........................................................................................................................5
P2. Explain using examples how different types of data can be converted and stored in
computer system..........................................................................................................................7
P3. Convert numeric data between different number systems including floating point..............9
LO2 Understand the functions of computer system components..................................................18
P5. Illustrate the key computer system components and how they interact..............................18
P6. Explain the different types of memory that can be attached to a processor........................21
P7. Explain how polling and interrupts are used to allow communication between processor
and peripherals...........................................................................................................................24
LO3 Understand the principles of processor operations................................................................25
P8. Compare Reduced Instruction Set Computer (RISC) chips and Complex Instruction Set
Computer (CISC) chips .............................................................................................................26
P9. Illustrate the use of the different processor registers in the fetch-execute cycle.................29
Conclusion.....................................................................................................................................32
References......................................................................................................................................33
1
List of Figures
Figure 1- Image representation........................................................................................................7
Figure 2- OR Gate.........................................................................................................................12
Figure 3- AND Gate......................................................................................................................12
Figure 4- NOT Gate.......................................................................................................................13
Figure 5- NAND Gate...................................................................................................................13
Figure 6- NOR Gate.......................................................................................................................14
Figure 7- XOR Gate.......................................................................................................................15
Figure 8- Combined Circuit...........................................................................................................15
Figure 9- Von-Neumann architecture............................................................................................18
Figure 10- Scanner.........................................................................................................................18
Figure 11- CPU..............................................................................................................................19
Figure 12- Program counter...........................................................................................................20
Figure 13- Printer...........................................................................................................................20
Figure 14- SRAM..........................................................................................................................21
Figure 15- DRAM..........................................................................................................................21
Figure 16- ROM............................................................................................................................21
Figure 17- Flash memory...............................................................................................................22
Figure 18- Cache Memory.............................................................................................................22
Figure 19- GPR..............................................................................................................................23
Figure 20- Polling..........................................................................................................................24
Figure 21- Occurrence of interrupts..............................................................................................24
Figure 22- Pipelining.....................................................................................................................25
Figure 23- Parallel processing.......................................................................................................25
Figure 24- Multiprocessing............................................................................................................25
Figure 25- CISC Architecture........................................................................................................26
Figure 26- RISC Architecture........................................................................................................27
Figure 27- Fetching........................................................................................................................30
Figure 28- Decoding and Storing Data..........................................................................................30
Figure 29- Execute.........................................................................................................................31
2
Figure 1- Image representation........................................................................................................7
Figure 2- OR Gate.........................................................................................................................12
Figure 3- AND Gate......................................................................................................................12
Figure 4- NOT Gate.......................................................................................................................13
Figure 5- NAND Gate...................................................................................................................13
Figure 6- NOR Gate.......................................................................................................................14
Figure 7- XOR Gate.......................................................................................................................15
Figure 8- Combined Circuit...........................................................................................................15
Figure 9- Von-Neumann architecture............................................................................................18
Figure 10- Scanner.........................................................................................................................18
Figure 11- CPU..............................................................................................................................19
Figure 12- Program counter...........................................................................................................20
Figure 13- Printer...........................................................................................................................20
Figure 14- SRAM..........................................................................................................................21
Figure 15- DRAM..........................................................................................................................21
Figure 16- ROM............................................................................................................................21
Figure 17- Flash memory...............................................................................................................22
Figure 18- Cache Memory.............................................................................................................22
Figure 19- GPR..............................................................................................................................23
Figure 20- Polling..........................................................................................................................24
Figure 21- Occurrence of interrupts..............................................................................................24
Figure 22- Pipelining.....................................................................................................................25
Figure 23- Parallel processing.......................................................................................................25
Figure 24- Multiprocessing............................................................................................................25
Figure 25- CISC Architecture........................................................................................................26
Figure 26- RISC Architecture........................................................................................................27
Figure 27- Fetching........................................................................................................................30
Figure 28- Decoding and Storing Data..........................................................................................30
Figure 29- Execute.........................................................................................................................31
2
List of Tables
Table 1- ASCII Table......................................................................................................................6
Table 2- OR gate truth table..........................................................................................................12
Table 3- AND gate Truth Table.....................................................................................................13
Table 4- NOT Gate Truth Table....................................................................................................13
Table 5- NAND Gate Truth Table.................................................................................................14
Table 6- NOR Gate Truth Table....................................................................................................14
Table 7- XOR Gate Truth Table....................................................................................................15
Table 8- Truth table.......................................................................................................................16
Table 9- CISC v/s RISC................................................................................................................28
3
Table 1- ASCII Table......................................................................................................................6
Table 2- OR gate truth table..........................................................................................................12
Table 3- AND gate Truth Table.....................................................................................................13
Table 4- NOT Gate Truth Table....................................................................................................13
Table 5- NAND Gate Truth Table.................................................................................................14
Table 6- NOR Gate Truth Table....................................................................................................14
Table 7- XOR Gate Truth Table....................................................................................................15
Table 8- Truth table.......................................................................................................................16
Table 9- CISC v/s RISC................................................................................................................28
3
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Introduction
Computer Architecture is a combined network of hardware and software to form a computer
system which defines a relation and connection between them. It characterizes how hardware and
software tools communicate with each other in a computer system. At present time most of the
system use this architecture principle. The most famous and reliable computer architecture is
Von Neumann Architecture and almost every system is designed on this architecture at present
time.
The purpose of this assignment is to establish the new subject of Computer Mathematics for
government-funded college. This subject is introduced to define that how computer machines are
performing various types of calculation and feeding the proper output as per the requirements. So
in this assignment, I had introduced topics like Von Neumann Architecture, conversions of
different base numbers, text, images, and videos into the low-level language which can be
understood by computer machine. Also, the fetch-execution cycle which defines the order of
execution of instructions in a system.
4
Computer Architecture is a combined network of hardware and software to form a computer
system which defines a relation and connection between them. It characterizes how hardware and
software tools communicate with each other in a computer system. At present time most of the
system use this architecture principle. The most famous and reliable computer architecture is
Von Neumann Architecture and almost every system is designed on this architecture at present
time.
The purpose of this assignment is to establish the new subject of Computer Mathematics for
government-funded college. This subject is introduced to define that how computer machines are
performing various types of calculation and feeding the proper output as per the requirements. So
in this assignment, I had introduced topics like Von Neumann Architecture, conversions of
different base numbers, text, images, and videos into the low-level language which can be
understood by computer machine. Also, the fetch-execution cycle which defines the order of
execution of instructions in a system.
4
LO1 Understand how data can be represented within computer systems
P1. Explain using examples how numeric and alphanumeric data can be coded
within a computer system
In order to conceptualize how different data is coded within a computer system, there is the need
to first understand what is numeric type data and alphanumeric data. Numeric data is the form of
information that can be represented in number form i.e. the information that can be countable
and can be represented in mathematical form. Some of the common examples are integers,
floating points and octal.
Integers: Integers are those which are whole in nature and uses base from 0 to 9. Hence
numbers formed ranges from 0 to trillions like 1, 56406, 89410512564231 etc.
Floating points: A number with a decimal is known as floating point number. Position of
decimal is not precise like 1.2, 1145.0641, 4785421.33. All these are an example of
floating point numbers (Corio, 2014).
Octal: Octal numbers are the number which uses base from 0 to 7. All the numbers
formed in octal system have base 8 (ElectronicsHub, 2015).
Alphanumeric data is the combination of alphabets and numbers. It comprises some special
symbols like *, @, #, & and characters representing 0-9 and a-z (both upper and lower case) and
Hexadecimal system is the best example of alphanumeric data. It uses base 16 i.e. numbers 0-9
and A to F uppercase letters to show its decimal numbers. For example, 16,295 can be
represented as 3FA7 in hexadecimal system (Jackson, 2017).
Computer understands binary language or binary system. It has 2 components that are 0s and 1s.
It is similar to our electric home switches just ON (represented by 1s) and OFF (by 0s). All the
instructions within systems are performed through bits (0 & 1 are bit) and a series of 8 bits is
called 1 Byte. All the data in a computer is stored in bits or combination of bits (Bytes), a
combination of bytes (Mega-Bytes MB) and so on. The process of interpreting raw 0s and 1s
and converting it into real character can be described as Character Encoding. There are many
different types of character encoding standards exist like ASCII (American Standard Code for
Information Interchange), ANSI (American National Standards Institute), Unicode and ASCII
being the first character encoding standard is widely used for representing English characters
5
P1. Explain using examples how numeric and alphanumeric data can be coded
within a computer system
In order to conceptualize how different data is coded within a computer system, there is the need
to first understand what is numeric type data and alphanumeric data. Numeric data is the form of
information that can be represented in number form i.e. the information that can be countable
and can be represented in mathematical form. Some of the common examples are integers,
floating points and octal.
Integers: Integers are those which are whole in nature and uses base from 0 to 9. Hence
numbers formed ranges from 0 to trillions like 1, 56406, 89410512564231 etc.
Floating points: A number with a decimal is known as floating point number. Position of
decimal is not precise like 1.2, 1145.0641, 4785421.33. All these are an example of
floating point numbers (Corio, 2014).
Octal: Octal numbers are the number which uses base from 0 to 7. All the numbers
formed in octal system have base 8 (ElectronicsHub, 2015).
Alphanumeric data is the combination of alphabets and numbers. It comprises some special
symbols like *, @, #, & and characters representing 0-9 and a-z (both upper and lower case) and
Hexadecimal system is the best example of alphanumeric data. It uses base 16 i.e. numbers 0-9
and A to F uppercase letters to show its decimal numbers. For example, 16,295 can be
represented as 3FA7 in hexadecimal system (Jackson, 2017).
Computer understands binary language or binary system. It has 2 components that are 0s and 1s.
It is similar to our electric home switches just ON (represented by 1s) and OFF (by 0s). All the
instructions within systems are performed through bits (0 & 1 are bit) and a series of 8 bits is
called 1 Byte. All the data in a computer is stored in bits or combination of bits (Bytes), a
combination of bytes (Mega-Bytes MB) and so on. The process of interpreting raw 0s and 1s
and converting it into real character can be described as Character Encoding. There are many
different types of character encoding standards exist like ASCII (American Standard Code for
Information Interchange), ANSI (American National Standards Institute), Unicode and ASCII
being the first character encoding standard is widely used for representing English characters
5
and integers as numbers, each letter assigned a value from 0-127 uniquely. ASCII defines 7-bit
code with total 128 (0-127) ASCII values. To extend these ANSI extend it to 8 bit and introduce
different code pages for symbols 128 to 255 whereas Unicode is a platform-independent internal
text coding system used in all computer system, whether it is Windows, Linux, Unix because it
can handle almost all languages. Now at present, we have worldwide accepted encoding
standard to process text and data into machine language. But how it is performed by the system.
Let's take the example of conversion of text into ASCII code. But before that, there is the need
of ASCII code table which is shown below:
Table 1- ASCII Table
Let's take an example to understand it better.
Example: RAT
Now to get ASCII code for “RAT”, look at the value of letters in above table. R=82, A=65,
T=84. Hence ASCII code for RAT will be 82 65 84 and its corresponding binary code is
00111000 00110010 00100000 00110110 00110101 00100000 00111000 00110100
6
code with total 128 (0-127) ASCII values. To extend these ANSI extend it to 8 bit and introduce
different code pages for symbols 128 to 255 whereas Unicode is a platform-independent internal
text coding system used in all computer system, whether it is Windows, Linux, Unix because it
can handle almost all languages. Now at present, we have worldwide accepted encoding
standard to process text and data into machine language. But how it is performed by the system.
Let's take the example of conversion of text into ASCII code. But before that, there is the need
of ASCII code table which is shown below:
Table 1- ASCII Table
Let's take an example to understand it better.
Example: RAT
Now to get ASCII code for “RAT”, look at the value of letters in above table. R=82, A=65,
T=84. Hence ASCII code for RAT will be 82 65 84 and its corresponding binary code is
00111000 00110010 00100000 00110110 00110101 00100000 00111000 00110100
6
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P2. Explain using examples how different types of data can be converted and stored
in computer system
Different data can be stored in computer system like images, audios, videos, text files and all the
specific type have a specific format. Images stored in JPEG (Joint Photographic Experts Group),
JPG (Joint Photographic Group), PNG (Portable Network Graphics), GIF (Graphics Interchange
Format). Similarly, audios in mp3 format and videos in mp4 and text files in various formats like
.txt, .doc depending on requirement. Different type of file format tells user about the file type
without opening it as well as to computer and then instruction is executed to process them. But
how all these are stored in computer and displayed to user (Fisher, 2018).
An image is a collection of small dots known as pixel. Thus a group of small illuminating dots
combined together form a picture or image and is stored in system in same way. But computer
stores all the things in binary system. Hence images are also stored in binary form where 0
represent white and 1 is black (Cooper, 2015).
Figure 1- Image representation
Source- (Computerscience, 2017)
Further combination of 0s and 1s produce different colours. Each and every colour of image is
stored as a binary number. A computer screen which shows images consist of thousands of pixels
7
in computer system
Different data can be stored in computer system like images, audios, videos, text files and all the
specific type have a specific format. Images stored in JPEG (Joint Photographic Experts Group),
JPG (Joint Photographic Group), PNG (Portable Network Graphics), GIF (Graphics Interchange
Format). Similarly, audios in mp3 format and videos in mp4 and text files in various formats like
.txt, .doc depending on requirement. Different type of file format tells user about the file type
without opening it as well as to computer and then instruction is executed to process them. But
how all these are stored in computer and displayed to user (Fisher, 2018).
An image is a collection of small dots known as pixel. Thus a group of small illuminating dots
combined together form a picture or image and is stored in system in same way. But computer
stores all the things in binary system. Hence images are also stored in binary form where 0
represent white and 1 is black (Cooper, 2015).
Figure 1- Image representation
Source- (Computerscience, 2017)
Further combination of 0s and 1s produce different colours. Each and every colour of image is
stored as a binary number. A computer screen which shows images consist of thousands of pixels
7
and different image quality depends on resolution aspect. Resolution of image is how compactly
pixels are bundled, loose and larger the pixels, blockier and blur will be the image and vice
versa. In a much similar manner, an audio file or a song you play on system is analysed and
processed. Since sound is a harmonic wave so it is first converted by processor of a computer
into analog signal and to process analog signals sampling rate is measured. Sampling rate is
twice the highest frequency in a wave. Highest frequency in a recording is called Nyquist
frequency. Sample rate value is plotted on y-axis by processor along with each time unit on x-
axis and is then processed and known as Time Value. These time value is converted into binary
numbers and hence processed. In the same way, a video is processed and played. Just like picture
and image have smallest entity pixel in the same way a video or moving image have the smallest
entity called frame. A digital film is formed from a series of images and these images are played
at high speed around 30 to 100 frames per second and hence fast-moving images sequentially
resultant into video. All the processed data is stored in memory of computer and hence it is a
limited resource. From time to time we need to clean up by deleting data or by compressing.
Compression can be done in two ways- Lossless and Lossy. In lossless compression, data quality
is not compromised and its format gets changed to reduce space like Zip file whereas in lossy
compression, quality is being diminished to reduce file size and original data might be lost
permanently.
8
pixels are bundled, loose and larger the pixels, blockier and blur will be the image and vice
versa. In a much similar manner, an audio file or a song you play on system is analysed and
processed. Since sound is a harmonic wave so it is first converted by processor of a computer
into analog signal and to process analog signals sampling rate is measured. Sampling rate is
twice the highest frequency in a wave. Highest frequency in a recording is called Nyquist
frequency. Sample rate value is plotted on y-axis by processor along with each time unit on x-
axis and is then processed and known as Time Value. These time value is converted into binary
numbers and hence processed. In the same way, a video is processed and played. Just like picture
and image have smallest entity pixel in the same way a video or moving image have the smallest
entity called frame. A digital film is formed from a series of images and these images are played
at high speed around 30 to 100 frames per second and hence fast-moving images sequentially
resultant into video. All the processed data is stored in memory of computer and hence it is a
limited resource. From time to time we need to clean up by deleting data or by compressing.
Compression can be done in two ways- Lossless and Lossy. In lossless compression, data quality
is not compromised and its format gets changed to reduce space like Zip file whereas in lossy
compression, quality is being diminished to reduce file size and original data might be lost
permanently.
8
P3. Convert numeric data between different number systems including floating
point
To convert any number into another system, we need to keep the base value of the resultant
system. Let's take few different examples of different conversions.
1. Decimal to binary conversion
Let's understand it with an example to convert 105 into binary. We will take base value of
binary system i.e. 2. For conversion, divide the decimal number (here 105) by base value
and note down the remainder and divide the quotient again. Repeat until the value
becomes less than base and the final result will be noted from downwards to upwards (as
shown below):
Base Values &
Quotient
Remainder
2 105 1
2 52 0
2 26 0
2 13 1
2 6 0
2 3 1
2 1
Hence Binary value of 105 is 1101001.
2. Binary to decimal
Let's take example again. Here decimal bases will be 1 2 4 8 16 32 i.e preceded number
multiplied by 2.
Binary Value 1 1 0 1 0 0 1
Decimal Value 64 32 1
6
8 4 2 1
Binary digit 1 is written corresponding decimal value and add all of them i.e.
64+32+8+1=105.
Hence 1101001 in decimal form is 105.
9
point
To convert any number into another system, we need to keep the base value of the resultant
system. Let's take few different examples of different conversions.
1. Decimal to binary conversion
Let's understand it with an example to convert 105 into binary. We will take base value of
binary system i.e. 2. For conversion, divide the decimal number (here 105) by base value
and note down the remainder and divide the quotient again. Repeat until the value
becomes less than base and the final result will be noted from downwards to upwards (as
shown below):
Base Values &
Quotient
Remainder
2 105 1
2 52 0
2 26 0
2 13 1
2 6 0
2 3 1
2 1
Hence Binary value of 105 is 1101001.
2. Binary to decimal
Let's take example again. Here decimal bases will be 1 2 4 8 16 32 i.e preceded number
multiplied by 2.
Binary Value 1 1 0 1 0 0 1
Decimal Value 64 32 1
6
8 4 2 1
Binary digit 1 is written corresponding decimal value and add all of them i.e.
64+32+8+1=105.
Hence 1101001 in decimal form is 105.
9
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3. Decimal to hexadecimal
To convert to hexadecimal take base value 16 and conversion is done in same way as
done in the conversion of decimal to binary. Divide the number by 16 till number is
greater than base and note remainder. In hexadecimal, base values from 0-9 and then after
A-F. A=10, B=11 C=12, D=13, E=14, F=15.
Base Remainder
16 170 10=A
16 10
Hence the hexadecimal equivalence for 170 is AA.
4. Hexadecimal to decimal
Let's take previous example AA. To convert from hexadecimal to decimal, successive
powers of 16 is multiplied by given number and add them.
10*(161) + 10*(160)
= 160 + 10
= 170
5. Floating point to Binary.
Floating point numbers are numbers with a decimal at a precise location. Example
105.625
First, we need to convert characteristic then mantissa separately using base value 2.
Base Values &
Quotient
Remainder
2 105 1
2 52 0
2 26 0
2 13 1
2 6 0
2 3 1
2 1
10
To convert to hexadecimal take base value 16 and conversion is done in same way as
done in the conversion of decimal to binary. Divide the number by 16 till number is
greater than base and note remainder. In hexadecimal, base values from 0-9 and then after
A-F. A=10, B=11 C=12, D=13, E=14, F=15.
Base Remainder
16 170 10=A
16 10
Hence the hexadecimal equivalence for 170 is AA.
4. Hexadecimal to decimal
Let's take previous example AA. To convert from hexadecimal to decimal, successive
powers of 16 is multiplied by given number and add them.
10*(161) + 10*(160)
= 160 + 10
= 170
5. Floating point to Binary.
Floating point numbers are numbers with a decimal at a precise location. Example
105.625
First, we need to convert characteristic then mantissa separately using base value 2.
Base Values &
Quotient
Remainder
2 105 1
2 52 0
2 26 0
2 13 1
2 6 0
2 3 1
2 1
10
Now we need to convert mantissa and while converting mantissa, base value is multiplied
to mantissa and characteristic is noted.
11
to mantissa and characteristic is noted.
11
Result
0.625*2 = 1.25 1
0.25*2=0.5 0
0.5*2=1.0 1
Hence (0.625) is represented as (101)2
(105.625)10 = (1101001.101)2
6. Binary to floating point
To convert to floating point, we need to follow certain defined steps.
Let’s take an example: 0.1010
= 1*(2-1) + 0*(2-2) + 1*(2-3) + 0*(2-4)
= 0.5 + 0 + 0.125 + 0
=0.625
So binary conversion of 0.1010 is 0.625
M1: In this section I have successfully convert numeric data system including the floating point.
12
0.625*2 = 1.25 1
0.25*2=0.5 0
0.5*2=1.0 1
Hence (0.625) is represented as (101)2
(105.625)10 = (1101001.101)2
6. Binary to floating point
To convert to floating point, we need to follow certain defined steps.
Let’s take an example: 0.1010
= 1*(2-1) + 0*(2-2) + 1*(2-3) + 0*(2-4)
= 0.5 + 0 + 0.125 + 0
=0.625
So binary conversion of 0.1010 is 0.625
M1: In this section I have successfully convert numeric data system including the floating point.
12
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P4. Carry out Boolean logic operations
1. OR Gate: OR gate perform addition and if any of input is logic 1, then output will be
logical 1
Figure 2- OR Gate
Source- (Josh, 2015)
Table 2- OR gate truth table
X Y Z (Output)
0 0 0
0 1 1
1 0 1
1 1 1
2. AND Gate: And gate produces output as logic 1 if all the inputs are logic 1.
Figure 3- AND Gate
Source- (Josh, 2015)
13
1. OR Gate: OR gate perform addition and if any of input is logic 1, then output will be
logical 1
Figure 2- OR Gate
Source- (Josh, 2015)
Table 2- OR gate truth table
X Y Z (Output)
0 0 0
0 1 1
1 0 1
1 1 1
2. AND Gate: And gate produces output as logic 1 if all the inputs are logic 1.
Figure 3- AND Gate
Source- (Josh, 2015)
13
Table 3- AND gate Truth Table
X Y Z (Output)
0 0 0
0 1 0
1 0 0
1 1 1
3. NOT Gate: It reverses the logic output.
Figure 4- NOT Gate
Source- (Josh, 2015)
Table 4- NOT Gate Truth Table
X Z (Output)
0 1
1 0
4. NAND Gate: It produces logic 1 if any of input is logic 0.
Figure 5- NAND Gate
Source- (Josh, 2015)
14
X Y Z (Output)
0 0 0
0 1 0
1 0 0
1 1 1
3. NOT Gate: It reverses the logic output.
Figure 4- NOT Gate
Source- (Josh, 2015)
Table 4- NOT Gate Truth Table
X Z (Output)
0 1
1 0
4. NAND Gate: It produces logic 1 if any of input is logic 0.
Figure 5- NAND Gate
Source- (Josh, 2015)
14
Table 5- NAND Gate Truth Table
X Y Z (Output)
0 0 1
0 1 1
1 0 1
1 1 0
5. NOR Gate: It is a combination of Not and Or gate.
Figure 6- NOR Gate
Source- (Josh, 2015)
Table 6- NOR Gate Truth Table
X Y Z (Output)
0 0 1
0 1 0
1 0 0
1 1 0
6. XOR Gate: If both the inputs are same then it will give logic 0.
15
X Y Z (Output)
0 0 1
0 1 1
1 0 1
1 1 0
5. NOR Gate: It is a combination of Not and Or gate.
Figure 6- NOR Gate
Source- (Josh, 2015)
Table 6- NOR Gate Truth Table
X Y Z (Output)
0 0 1
0 1 0
1 0 0
1 1 0
6. XOR Gate: If both the inputs are same then it will give logic 0.
15
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Figure 7- XOR Gate
Source- (Josh, 2015)
Table 7- XOR Gate Truth Table
X Y Z (Output)
0 0 0
0 1 1
1 0 1
1 1 0
Now understand all the gates by combining together to understand how they work.
Figure 8- Combined Circuit
16
Source- (Josh, 2015)
Table 7- XOR Gate Truth Table
X Y Z (Output)
0 0 0
0 1 1
1 0 1
1 1 0
Now understand all the gates by combining together to understand how they work.
Figure 8- Combined Circuit
16
Table 8- Truth table
A B C D E F G H I Z
0 0 0 0 0 0 0 1 0 1
0 0 0 1 0 1 1 0 0 1
0 0 1 0 0 1 1 1 0 1
0 0 1 1 0 1 1 0 0 1
0 1 0 0 0 0 0 1 0 1
0 1 0 1 0 1 1 0 0 1
0 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 1 0 0 1
1 0 0 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0 0 1
1 0 1 0 0 1 1 1 0 1
1 0 1 1 0 1 1 0 0 1
1 1 0 0 1 0 1 1 0 1
1 1 0 1 1 1 0 0 1 1
1 1 1 0 1 1 0 1 0 1
1 1 1 1 1 1 0 0 1 1
In the above-explained gates, we have taken four inputs i.e. A, B, C, D corresponding to which E
is output performing A AND B and F perform C OR D gate. Output E and F becomes input to
17
A B C D E F G H I Z
0 0 0 0 0 0 0 1 0 1
0 0 0 1 0 1 1 0 0 1
0 0 1 0 0 1 1 1 0 1
0 0 1 1 0 1 1 0 0 1
0 1 0 0 0 0 0 1 0 1
0 1 0 1 0 1 1 0 0 1
0 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 1 0 0 1
1 0 0 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0 0 1
1 0 1 0 0 1 1 1 0 1
1 0 1 1 0 1 1 0 0 1
1 1 0 0 1 0 1 1 0 1
1 1 0 1 1 1 0 0 1 1
1 1 1 0 1 1 0 1 0 1
1 1 1 1 1 1 0 0 1 1
In the above-explained gates, we have taken four inputs i.e. A, B, C, D corresponding to which E
is output performing A AND B and F perform C OR D gate. Output E and F becomes input to
17
XOR gate and produces G which is one input to NOR gate and other input of H which is output
of NOT gate. Finally, I and H becomes input to NAND gate and produces final output Z.
18
of NOT gate. Finally, I and H becomes input to NAND gate and produces final output Z.
18
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LO2 Understand the functions of computer system components
P5. Illustrate the key computer system components and how they interact
Von Neumann Architecture:
Figure 9- Von-Neumann architecture
Source- (joeyang99, 2016)
Von Neumann Architecture defines the connection between the various components of computer
like input devices, CPU, memory unit and output devices. It was first given by John von
Neumann in 1945. This architecture is divided into various parts. Let us discuss each in detail:
Input Devices: The devices that takes the input from user and on which processing is done. For
example scanner, mouse, keyboard and joystick.
Figure 10- Scanner
19
P5. Illustrate the key computer system components and how they interact
Von Neumann Architecture:
Figure 9- Von-Neumann architecture
Source- (joeyang99, 2016)
Von Neumann Architecture defines the connection between the various components of computer
like input devices, CPU, memory unit and output devices. It was first given by John von
Neumann in 1945. This architecture is divided into various parts. Let us discuss each in detail:
Input Devices: The devices that takes the input from user and on which processing is done. For
example scanner, mouse, keyboard and joystick.
Figure 10- Scanner
19
Central Processing Unit: CPU is the major and most important component of the system. It
consists of control unit, registers, arithmetic and logical unit.
Figure 11- CPU
Control Unit: It is the part of architecture of central processing unit which tells the processor
about its task and directs the processor what to do next.
Arithmetic and Logical Unit: It is another component of a central processing unit used to
perform arithmetic operations such as addition, multiplication, subtraction and division and logic
operations such as AND, OR, XOR, NAND and more.
Registers: Registers are the part of CPU basically used for storage purpose. It consists of address
of memory location as well as data also. When flip-flops are grouped together it converts into
register. There are many types of register each having its own functionality and use. Following
registers are:
Accumulator register(AC): It is used for storing the result produced by the system.
Program counter(PC): It is basically used for pointing towards next instruction address or next
memory address.
20
consists of control unit, registers, arithmetic and logical unit.
Figure 11- CPU
Control Unit: It is the part of architecture of central processing unit which tells the processor
about its task and directs the processor what to do next.
Arithmetic and Logical Unit: It is another component of a central processing unit used to
perform arithmetic operations such as addition, multiplication, subtraction and division and logic
operations such as AND, OR, XOR, NAND and more.
Registers: Registers are the part of CPU basically used for storage purpose. It consists of address
of memory location as well as data also. When flip-flops are grouped together it converts into
register. There are many types of register each having its own functionality and use. Following
registers are:
Accumulator register(AC): It is used for storing the result produced by the system.
Program counter(PC): It is basically used for pointing towards next instruction address or next
memory address.
20
.
Figure 12- Program counter
Memory address register(MAR): It includes address of the next instructions.This register is
used for accessing instructions and data dynamically.
Memory data register (MDR): It has the data that is to be stored or fetched from the computer
storage. It holds the information before it goes to the decoder.
Memory unit: It is the storage component of CPU. In this, all the data and instructions are
stored. It can be of type RAM, ROM or cache memory.
Output Devices: These devices give the required data and information as output after processing
of input is done. Examples are a monitor, printer, speaker, webcam and many more.
Figure 13- Printer
21
Figure 12- Program counter
Memory address register(MAR): It includes address of the next instructions.This register is
used for accessing instructions and data dynamically.
Memory data register (MDR): It has the data that is to be stored or fetched from the computer
storage. It holds the information before it goes to the decoder.
Memory unit: It is the storage component of CPU. In this, all the data and instructions are
stored. It can be of type RAM, ROM or cache memory.
Output Devices: These devices give the required data and information as output after processing
of input is done. Examples are a monitor, printer, speaker, webcam and many more.
Figure 13- Printer
21
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P6. Explain the different types of memory that can be attached to a processor
Random Access Memory: RAM is a tempory memory. The data should be refreshed and saved
in order to protect the loss of data. It is of two types:
SRAM: Static RAM needs not to be refreshed. It is a true random access with less density with
high power and fast speed also having a con that is expensive.
Figure 14- SRAM
DRAM: Dynamic RAM need to be refreshed in less than 1 second it is not a true random access
with a low power and speed also having one pro that is cheaper in price.
Figure 15- DRAM
ROM: Read Only Memory is a permanent memory. It is the memory that cannot be an edit that
is it is only in readable format.It is mainly used for updating firmware.
Figure 16- ROM
22
Random Access Memory: RAM is a tempory memory. The data should be refreshed and saved
in order to protect the loss of data. It is of two types:
SRAM: Static RAM needs not to be refreshed. It is a true random access with less density with
high power and fast speed also having a con that is expensive.
Figure 14- SRAM
DRAM: Dynamic RAM need to be refreshed in less than 1 second it is not a true random access
with a low power and speed also having one pro that is cheaper in price.
Figure 15- DRAM
ROM: Read Only Memory is a permanent memory. It is the memory that cannot be an edit that
is it is only in readable format.It is mainly used for updating firmware.
Figure 16- ROM
22
ROM is classified into three types:
Programmable Read-Only Memory (PROM): This memory can be reconfigured. It can be
updated once.
Erasable Programmable Read-Only Memory (EPROM): Memory can be erased using
ultraviolet rays and again reprogrammable. Updating can be done more than once.
Electrically Erasable Programmable Read-Only Memory (EEPROM): It is a flash memory.
It can be electronically erased and then it can be reconfigured again.
Figure 17- Flash memory
Cache Memory:
Cache memory is a type of RAM that can be easily and quickly accessible compared to other
memories it is expensive in nature it is directly connected to the central processing unit which
makes it easily accessible.
Figure 18- Cache Memory
It is divided into three levels. They are:
23
Programmable Read-Only Memory (PROM): This memory can be reconfigured. It can be
updated once.
Erasable Programmable Read-Only Memory (EPROM): Memory can be erased using
ultraviolet rays and again reprogrammable. Updating can be done more than once.
Electrically Erasable Programmable Read-Only Memory (EEPROM): It is a flash memory.
It can be electronically erased and then it can be reconfigured again.
Figure 17- Flash memory
Cache Memory:
Cache memory is a type of RAM that can be easily and quickly accessible compared to other
memories it is expensive in nature it is directly connected to the central processing unit which
makes it easily accessible.
Figure 18- Cache Memory
It is divided into three levels. They are:
23
Level 1 cache: It is directly attached to the processor chip. It is fast and size is small in few Kb
only.
Level 2 cache: Its capacity lies between 64 Kb to 16 Mb. It is advance cache on processing chip
for transfer of data.
Level 3 cache: It is outside of processor chip. It only appears in the L2 advance cache of a
computer machine. In computers, it exceeds up to 8 Mb.
Registers:
General Purpose Register: Registers that are more efficient to use by the compiler. It reduces
the traffic by holding the variables. It is based on the load-store register architecture.
Figure 19- GPR
Special Purpose Register: These registers include PC, ACC, MAR, MDR and many more
registers. Unlike general purpose register, it permanently holds the variable and data. Instruction
pointer is used for pointing the data and instruction that need to be done in further step it points
towards the address that contains further instructions.
M2, D1: Different types of memory like RAM, ROM and cache memory which can be
connected to the processor easily.
24
only.
Level 2 cache: Its capacity lies between 64 Kb to 16 Mb. It is advance cache on processing chip
for transfer of data.
Level 3 cache: It is outside of processor chip. It only appears in the L2 advance cache of a
computer machine. In computers, it exceeds up to 8 Mb.
Registers:
General Purpose Register: Registers that are more efficient to use by the compiler. It reduces
the traffic by holding the variables. It is based on the load-store register architecture.
Figure 19- GPR
Special Purpose Register: These registers include PC, ACC, MAR, MDR and many more
registers. Unlike general purpose register, it permanently holds the variable and data. Instruction
pointer is used for pointing the data and instruction that need to be done in further step it points
towards the address that contains further instructions.
M2, D1: Different types of memory like RAM, ROM and cache memory which can be
connected to the processor easily.
24
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P7. Explain how polling and interrupts are used to allow communication between
processor and peripherals
Polling:
Polling is the procedure in which the system or device waits for the external device to check the
status with low-level hardware. In polling, the previous program checks it precedence program
and this cycles go on for next.
Figure 20- Polling
Interrupts:
Interrupts in the system is a kind of error or alert that needs to attend first. It comes in the form of
signal to the system either from hardware or software. Interrupts are always kept on the highest
priority.
Figure 21- Occurrence of interrupts
Communication Process:
Core is defined as the component having two or more independent processing unit in
processor.in core, we can run a single program maintaining all other factors.
25
processor and peripherals
Polling:
Polling is the procedure in which the system or device waits for the external device to check the
status with low-level hardware. In polling, the previous program checks it precedence program
and this cycles go on for next.
Figure 20- Polling
Interrupts:
Interrupts in the system is a kind of error or alert that needs to attend first. It comes in the form of
signal to the system either from hardware or software. Interrupts are always kept on the highest
priority.
Figure 21- Occurrence of interrupts
Communication Process:
Core is defined as the component having two or more independent processing unit in
processor.in core, we can run a single program maintaining all other factors.
25
Single core: It is a type of microprocessor that has only one thread executing at a time.
Multiple cores: It is a type in which more than one thread executes at a time. When we overlap
multiple instructions dynamically that is o execution time than this technique is called
pipelining.
Figure 22- Pipelining
Parallel Processing: It is the procedure or technique of dividing the instruction into multiple
threads and run them parallel on multiple processors.
Figure 23- Parallel processing
Multiprocessing: It is different in the sense that in this process multiple central processing units
are attached to a single system and then the instructions are followed.
Figure 24- Multiprocessing
LO3 Understand the principles of processor operations
26
Multiple cores: It is a type in which more than one thread executes at a time. When we overlap
multiple instructions dynamically that is o execution time than this technique is called
pipelining.
Figure 22- Pipelining
Parallel Processing: It is the procedure or technique of dividing the instruction into multiple
threads and run them parallel on multiple processors.
Figure 23- Parallel processing
Multiprocessing: It is different in the sense that in this process multiple central processing units
are attached to a single system and then the instructions are followed.
Figure 24- Multiprocessing
LO3 Understand the principles of processor operations
26
P8. Compare Reduced Instruction Set Computer (RISC) chips and Complex
Instruction Set Computer (CISC) chips .
A CPU of the computer can be differentiated on the bases of a number of instruction cycles
performed, clock speed, registers, energy consumed. Upon on these factors, there are two types
of CPU- CISC (Complex Instructing Set Computing) and RISC (Reduced Instructing Set
Computing).
CISC-
Primary goal of CISC architecture is to execute and process task in few lines as much as
possible. It can be achieved by designing processor hardware capable of executing multiple
sequential instructions. For this, processor is embedded with a specific instruction “MULT”.
This instruction can load values into different registers, execute multiply operation and store
result at desired register. MULT is an example of complex instruction. Hence many other
complex instructions lead to execution of multiple instructions at the same time, resulting in
fewer memory registers requirement. It also reduces number of cycles per instruction, thus
making instructions more complex.
CISC Architecture and how it performs instructions
Figure 25- CISC Architecture
Source:(Agarwal, 2015)
CISC uses minimum instruction and executes operation. Hence instruction generated by control
unit is flown to instruction set or data path where they are directed to computer by manipulating
27
Instruction Set Computer (CISC) chips .
A CPU of the computer can be differentiated on the bases of a number of instruction cycles
performed, clock speed, registers, energy consumed. Upon on these factors, there are two types
of CPU- CISC (Complex Instructing Set Computing) and RISC (Reduced Instructing Set
Computing).
CISC-
Primary goal of CISC architecture is to execute and process task in few lines as much as
possible. It can be achieved by designing processor hardware capable of executing multiple
sequential instructions. For this, processor is embedded with a specific instruction “MULT”.
This instruction can load values into different registers, execute multiply operation and store
result at desired register. MULT is an example of complex instruction. Hence many other
complex instructions lead to execution of multiple instructions at the same time, resulting in
fewer memory registers requirement. It also reduces number of cycles per instruction, thus
making instructions more complex.
CISC Architecture and how it performs instructions
Figure 25- CISC Architecture
Source:(Agarwal, 2015)
CISC uses minimum instruction and executes operation. Hence instruction generated by control
unit is flown to instruction set or data path where they are directed to computer by manipulating
27
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data. Instructions consist of Opcode (Operational code) and operand. Opcode is the main
instruction to be applied to data and operand is a memory register where instruction is applied.
And final result is stored in Main memory.
Example of CISC processor: IBM 370/168, Intel 80486.
RISC-
Although CISC reduces memory uses at the cost of complex instructions whereas in RISC
architecture instruction sets are simple and reduce execution time. Speed of execution is
accelerated using a various small number of instructions and these instructions are passed using
registers and local variables. For efficient usage of registers, reduced instruction set is used and
this can be achieved using pipeline technique which uses multiple parts of instruction
simultaneously so that every instruction is optimized.
RISC Architecture and how it performs instructions
Figure 26- RISC Architecture
Source:(Agarwal, 2015)
The main aim of RISC processor is the fast execution of instructions. Hence separate memory
cache is used to store instruction set and data. Instructions are fetched from instruction cache if
28
instruction to be applied to data and operand is a memory register where instruction is applied.
And final result is stored in Main memory.
Example of CISC processor: IBM 370/168, Intel 80486.
RISC-
Although CISC reduces memory uses at the cost of complex instructions whereas in RISC
architecture instruction sets are simple and reduce execution time. Speed of execution is
accelerated using a various small number of instructions and these instructions are passed using
registers and local variables. For efficient usage of registers, reduced instruction set is used and
this can be achieved using pipeline technique which uses multiple parts of instruction
simultaneously so that every instruction is optimized.
RISC Architecture and how it performs instructions
Figure 26- RISC Architecture
Source:(Agarwal, 2015)
The main aim of RISC processor is the fast execution of instructions. Hence separate memory
cache is used to store instruction set and data. Instructions are fetched from instruction cache if
28
present and data from data cache and then process instructions and final result are stored in main
memory. RISC processor contains a large number of registers so as to minimize interaction with
main memory. Hence more RAM is required to store assembly instruction (Studytonight, 2018).
Example of RISC processor: ARM (Advanced RISC Machine), Apple iPod.
Major Differences in CISC and RISC Processors
Although the main aim of all the processors is to execute the instruction and utilize the resources
optimally but below are the few differences between CISC and RISC.
Table 9- CISC v/s RISC
Architectural
Characteristics
CISC RISC
Instruction Nature Complex Nature Simple and reduced
instructions
Instruction Size Multiple size and formats(16-
64 bits per instruction).
Same set of instructions with
fixed format of 32 bit
Instruction Type Register Independent Register-based instructions.
CPU Control Uses control memory(ROM) Mostly hardwired without
control memory.
Architectural Orientation More importance to hardware. Software orientated.
29
memory. RISC processor contains a large number of registers so as to minimize interaction with
main memory. Hence more RAM is required to store assembly instruction (Studytonight, 2018).
Example of RISC processor: ARM (Advanced RISC Machine), Apple iPod.
Major Differences in CISC and RISC Processors
Although the main aim of all the processors is to execute the instruction and utilize the resources
optimally but below are the few differences between CISC and RISC.
Table 9- CISC v/s RISC
Architectural
Characteristics
CISC RISC
Instruction Nature Complex Nature Simple and reduced
instructions
Instruction Size Multiple size and formats(16-
64 bits per instruction).
Same set of instructions with
fixed format of 32 bit
Instruction Type Register Independent Register-based instructions.
CPU Control Uses control memory(ROM) Mostly hardwired without
control memory.
Architectural Orientation More importance to hardware. Software orientated.
29
P9. Illustrate the use of the different processor registers in the fetch-execute cycle
Fetch execution cycle or instruction cycle is the sequential steps executed by computer system to
perform specific process or task successfully. Execution cycle mainly divided into 3 sub-cycles
i.e. Fetch, Decode and Execute. First part of cycle deals with fetching the instructions from CPU
while in the second step fetched instruction is decoded by ALU (Arithmetic Logic Unit) and in
the final step, decoded part is executed and result is written back to register and then into
memory from registers. To understand the working of each sub-cycle, we first need to
understand some CPU registers name and their functionality.
MAR: Memory Access Register is the register used to store the address of memory for
reading and writing the opcode.
MBR: Memory Buffer Register keeps the information that is to be sent and received
from memory.
AC: Accumulator keeps track and stores the data which is being worked on through
ALU.
PC: Register used to hold the address of next program instruction is called Program
Counter. It is not connected to memory directly but via MAR.
IR: As soon as the data is read from memory, it first goes to MBR and if it is instruction,
then it moved to instruction register.
CU: Control Unit Register decodes the program instruction in IR (Robots, 2015).
Let's understand complete fetch cycle by taking an example of adding two numbers.
Fetch: This is the first and foremost step in any execution cycle. CPU reads stored a memory
address in PC register then shift it into MAR and value of PC incremented and now it points to
next instruction. Within a fraction of a section, data from MAR is copied to IR. Once data is in
IR, it decides which type of instruction it is and what instruction to be performed.
30
Fetch execution cycle or instruction cycle is the sequential steps executed by computer system to
perform specific process or task successfully. Execution cycle mainly divided into 3 sub-cycles
i.e. Fetch, Decode and Execute. First part of cycle deals with fetching the instructions from CPU
while in the second step fetched instruction is decoded by ALU (Arithmetic Logic Unit) and in
the final step, decoded part is executed and result is written back to register and then into
memory from registers. To understand the working of each sub-cycle, we first need to
understand some CPU registers name and their functionality.
MAR: Memory Access Register is the register used to store the address of memory for
reading and writing the opcode.
MBR: Memory Buffer Register keeps the information that is to be sent and received
from memory.
AC: Accumulator keeps track and stores the data which is being worked on through
ALU.
PC: Register used to hold the address of next program instruction is called Program
Counter. It is not connected to memory directly but via MAR.
IR: As soon as the data is read from memory, it first goes to MBR and if it is instruction,
then it moved to instruction register.
CU: Control Unit Register decodes the program instruction in IR (Robots, 2015).
Let's understand complete fetch cycle by taking an example of adding two numbers.
Fetch: This is the first and foremost step in any execution cycle. CPU reads stored a memory
address in PC register then shift it into MAR and value of PC incremented and now it points to
next instruction. Within a fraction of a section, data from MAR is copied to IR. Once data is in
IR, it decides which type of instruction it is and what instruction to be performed.
30
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Figure 27- Fetching
Source:(Ayoma, 2011)
Decode: Once the data is fetched and stored in IR, now CPU shifts data from IR to ALU through
data buses where certain decoding operations are performed. Depending upon the instructions to
be performed, different arithmetic operations are performed by ALU on opcode and operand.
Figure 28- Decoding and Storing Data
Source:(Ayoma, 2011)
Execute: After the fetching sub-cycle, an opcode is stored into IR and is decoded by control unit.
As of now, CU knows which instruction to perform and perform desired operations and hence so
produced output is again stored back in MBR register and MBR to main memory.
31
Source:(Ayoma, 2011)
Decode: Once the data is fetched and stored in IR, now CPU shifts data from IR to ALU through
data buses where certain decoding operations are performed. Depending upon the instructions to
be performed, different arithmetic operations are performed by ALU on opcode and operand.
Figure 28- Decoding and Storing Data
Source:(Ayoma, 2011)
Execute: After the fetching sub-cycle, an opcode is stored into IR and is decoded by control unit.
As of now, CU knows which instruction to perform and perform desired operations and hence so
produced output is again stored back in MBR register and MBR to main memory.
31
Figure 29- Execute
Source:(Ayoma, 2011)
M3, D2: In this section different type of processor register is used in describing the fetch-execute
cycle.
32
Source:(Ayoma, 2011)
M3, D2: In this section different type of processor register is used in describing the fetch-execute
cycle.
32
Conclusion
I had successfully completed and prepared the syllabus of “Computer Mathematics” subject for
the government-funded college. In this assignment, I had given the detailed description of
various topics provided to us. I had explored various websites, books, and tools to enhance the
knowledge of learning of students. Computer Architecture defines the relation between hardware
and software and how they interact in a system.
So in this assignment, I had discussed the Von Neumann Architecture and its working with a
conceptual diagram, various type of conversions with the help of an example, different types of
memory and their functionality, the role of CPU, polling and interrupt, the comparison between
RISC and CISC architecture and fetch-execute cycle in detail. For a logic diagram, I had used
Logic Circuit tool. I had discussed all the required information for the subject in a specific order
so that learning will be easier with each step. I had gathered the information and provided the
separate link to each topic which can help students to groom their knowledge.
33
I had successfully completed and prepared the syllabus of “Computer Mathematics” subject for
the government-funded college. In this assignment, I had given the detailed description of
various topics provided to us. I had explored various websites, books, and tools to enhance the
knowledge of learning of students. Computer Architecture defines the relation between hardware
and software and how they interact in a system.
So in this assignment, I had discussed the Von Neumann Architecture and its working with a
conceptual diagram, various type of conversions with the help of an example, different types of
memory and their functionality, the role of CPU, polling and interrupt, the comparison between
RISC and CISC architecture and fetch-execute cycle in detail. For a logic diagram, I had used
Logic Circuit tool. I had discussed all the required information for the subject in a specific order
so that learning will be easier with each step. I had gathered the information and provided the
separate link to each topic which can help students to groom their knowledge.
33
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References
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34
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[Accessed 17 Jan. 2018].
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ImageRepresentation.html [Accessed 17 Jan. 2018].
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at: https://www.techwalla.com/articles/why-is-a-file-extension-important [Accessed 17 Jan.
2018].
Corio, P. (2014). What's the difference between numeric data types, numeric value types and
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difference-between-numeric-data-types-numeric-value-types-and-url-data-types [Accessed
17 Jan. 2018].
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[Accessed 17 Jan. 2018].
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https://joeyang99.wordpress.com/2016/10/13/a-reflection-of-cpu-alu-cu-and-registers/
[Accessed 17 Jan. 2018].
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https://blog.digilentinc.com/logic-gates/ [Accessed 17 Jan. 2018].
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