Data Representation and Digital Logic

This assignment explores data representation using the IEEE-754 single precision format and covers the conversion of binary to decimal values. It also delves into signed binary number representations in signed magnitude, one's complement, and two's complement systems. Additionally, students are tasked with designing a logic circuit using basic gates to control a main entrance door based on time intervals, employing a 24-hour clock format.

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Subject Code (ITC544)
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(Assignment 1: Data Representation and Digital Logic)
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Question 1
(a)
A computer uses IEEE-754 single precision format to represent floating point. What value (in
decimal) does the computer represent if the floating point is represented using the following
binary digits. (6 marks)
0 01111110 10100000000000000000000
Solution
To convert from IEEE-754 to decimal, it is important to note that,
(i) The first term determines the sign of the number, the second term determines the
exponent, while the third term determines the fraction or the mantissa.
(ii) When the first term is 0 it is a positive number, if it is a 1 it is a negative number.
(iii) Determine the exponent by converting the binary octet to decimal value. Since, the
binary set is a single-precision number, subtract the exponent from the bias of 127.
(iv) The third term or the mantissa is converted to a fraction in base ten.
(v) The resultant syntax of conversion is,
( −1 ) sign bit∗( 1+fraction ) ∗sexponent−bias
The binary digits are signed 0 meaning it is a positively signed number.
The next section is 01111110 which is converted to decimal to represent the number,
011111102=12610
The mantissa is given by,
. 101000000000000000000002=.524288010
e=12610−12710=−110
¿ ( −1 ) 0∗( 1+ 0.625 )∗2−1
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¿ 1.625∗1
2 =0.812510
therefore ,the value stored ∈float is :0.8125
(b) Using a ‘word’ of 5 bits, list all of the possible signed binary numbers and their decimal
equivalents that are representable in
(i) signed magnitude
¿+1510 ¿−1510
¿ 011112 ¿111112
(ii) one’s complement
The negative number is retained and the positive number is complemented,
the range is [−15,15 ]10
¿ 111112 ¿ 100002
(iii) Two’s complement
the range is ¿ [−16,15 ]10
¿ 011112 ¿100002
Question 2
(a)
Write a Boolean function and construct a logic diagram of a circuit which use of basic logic
gates to activate CSU main entrance door during 9:00 am to 12:00 pm and after lunch time
during 1:00 pm - 4:00 pm. You need to use 24-hour clock timing when designing this circuit.
Solution
There are several occasions when the CSU main entrance door lock is locked.
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(i) when the manual switch is closed
(ii) when the input of the timer is 1 and when the timer is reset
When the time is in between the two set time ranges, that is between the 1 and 0 input we
demonstrate a case of access monitoring at the main entrance door. The circuit demonstrates the
use of XOR (Exclusive-OR) gates as bit comparators. There are four of these XOR gates
compare to the four bits that picks values from the system clock that operates in 24-hour format.
There are sixteen possible combinations for the 4-bit input keys so the lock is not very
complicated. It stores a memory that ensures that during the lunch break, the doors remain open.
But in the other session, the main entrance door remains locked.
(b) Boolean simplification
X' Y + XY Z' + Y ' + XZ ( Y +Y ' )=1
The simplification of the Boolean equation is,
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Considering , Y +Y ' =1
X' Y + XY Z' + Y '+ XZ=1
¿ the first two terms , Y is common ,Y ( X' +X Z' )
Y ( X' + X Z' )+Y ' +XZ=1
Introducing Z in the first term,
Y ( X' Z +X' Z' + X Z' ) +Y ' +XZ=1
But,
X' Z + X Z' = X ⊕Z ….. exclusive∨¿
Y ( X' Z' ( X ⊕ Z )+ XZ )+ X Y ' Z+ Y '=1
X' Z' ( X ⊕ Z ) =0
Y ( 0 ) +Y ' + XZ=1
∴ Y '+ XZ=1
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