Evolution of Computer Architecture

This paper discusses the evolution of computer architecture and its impact on performance. It explores concepts such as RISC architecture, pipelining, cache memory, and virtual memory.

Running head: COMPUTER ARCHITECTURE
Computer Architecture
Name of the Student
Name of the University
Author Note

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Evolution of the Computer System:
In the recent decades the computer system has been improved drastically. Comparing
current generation computers with some older computers there is a huge difference between
performances of them. The current generation computers are way stronger in the comparison.
The current computer system is capable of providing this high amount of performance due to
the changes in architectural designs from the last 25 years. For improving the performance of
the computers there are several of concepts which need to be improved and that are the
pipelining, RISC, cache memory and the virtual memory. In this paper how this concepts has
been evolved with the time will be discussed which are the main reasons of improvements in
the computer systems.
Evolution of the RISC Architecture: RISC is stand for Reduced Instruction Set Computer.
First this RISC chips were produced around mid-1980s which was a design strategy for the
CPUs. On that time the main advantage of the RISC architecture was that it was consisting
low amount of transistor due to which it was very much easy to build and with that it was
very much cost effective, but this less amount of transistors was also the main reason of its
low computing power (Waterman, 2016). There are various of designs that were proposed for
the RISC architecture from the 1960 and it still continuing now. One of the popular
architecture in this case was SPARC architecture. IBM also announced their RISC
architectures in 1990 and in 1993 which was actually improving with the time. For first 15
years performance of the microprocessors improved by on an average 35% per year and this
was possible due to the improvements in the RISC architectures.
Pipelining: In the case of computing the pipelining is also considered as the data pipelining.
It is actually some sets of data processing elements which all are connected in series.
Elements of the pipeline are executed in parallel fashion. In computing the main pipelining

2COMPUTER ARCHITECTURE
are the graphics pipelining, instruction pipelining, HTTP pipelining and the software
pipelining. The first general purpose pipelining machine was the Stretch which was the IBM
7030 in 1959. This machine was followed the IBM 704 and it was having a goal of having
100 times faster than the 704 (Pantazi-Mytarelli, 2013). In the previous times the Stanford
types of MIPS architecture has made the structure of pipeline visible directly to the compiler
and provided permission to perform multiple operations per instruction. In the previous
designs of the pipelining simple type of scheduling schemes were utilised. In previous
generation of pipelining techniques there were various types of issues regarding the
hardware. In the current scenario the system of pipelining has been improved much more.
Due to this improved pipelining system currently cycle time for the processes are reduced in
a greater a margin. The systems has become more reliable due to this improved pipelining
system that is evolving from last few decades. Also, current pipelining is able to increase the
system throughput.
Cache Memory: In computer system first cache memory was utilised at the timeframe of
386DX. At that time there was no integrated cache memory inside the CPU. Instead of the
CPU chipset was having a memory cache controller. Thus it indicates that at the initial stage
of the computing cache memory was external to the CPU thus it means that it was an optional
thing. Without the cache memory the PC will become much slower. The cache memory first
introduced as integrated with CPU with the Intel 486DX processors which was having 8 KB
of cache memory (Hager et al., 2018). This structure of the cache memory evolved with the
Pentium processors by Intel which was having two separate internal type of memory cache.
Here one of them was for instructions and another one was for the data. At this time two
levels of the memory cache was available which were L1 and L2. AMD in this segment
introduced third level of cache memory which was L3. At that time L2 cache was external
and due to that there was various of problems. With P6 architecture Intel moved this cache

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memory within CPU and this technology is still used in the present time. Though the
technology is the same, total size of this L1, L2 and this L3 cache memory has been increased
drastically in present time.
Virtual Memory: Virtual memory is also an important concept of computing which has been
evolved with time. Before introduction of the virtual memory computers was only having
primary memories (RAM) and secondary memory (Storage Devices). Initially this RAMs
were very much costly and also there was shortage in supply. This the main reason that the
virtual memory was introduced as at that times RAMs were not sufficient for handling all the
programs. The concept of virtual memory introduced with overlaying process. In 1969 it is
demonstrated by the IBM engineers that computers can perform better with the virtual
memory and from 1970 the virtual memory was in use. In 1982 Intel provided virtual
memory with 80286 processors and in 1985 it again provided paging support with the 80386
processor using virtual memory (Seshadri et al., 2016). Current this technology is utilised by
many computer systems for improving the overall system in case of shortage of primary
memory. The amount of the virtual memory is also increased with the time.

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References:
Hager, G., Eitzinger, J., Hornich, J., Cremonesi, F., Alappat, C. L., Röhl, T., & Wellein, G.
(2018). Applying the Execution-Cache-Memory Model: Current State of Practice.
Pantazi-Mytarelli, I. (2013, May). The history and use of pipelining computer architecture:
MIPS pipelining implementation. In 2013 IEEE Long Island Systems, Applications
and Technology Conference (LISAT) (pp. 1-7). IEEE.
Seshadri, V., Pekhimenko, G., Ruwase, O., Mutlu, O., Gibbons, P. B., Kozuch, M. A., ... &
Chilimbi, T. (2016). Page overlays: An enhanced virtual memory framework to
enable fine-grained memory management. ACM SIGARCH Computer Architecture
News, 43(3), 79-91.
Waterman, A. S. (2016). Design of the RISC-V instruction set architecture (Doctoral
dissertation, UC Berkeley).