DIGITAL & ANALOGUE DEVICES & CIRCUITS Assignment 3

MODULE TITLE : DIGITAL & ANALOGUE DEVICES & CIRCUITS
TOPIC TITLE : DIGITAL DEVICES & CIRCUITS
TUTOR MARKED ASSIGNMENT 3 (v1.1)
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DADC - 3 - TMA (v1.1)
© Teesside University 2011

Published by Teesside University Open Learning (Engineering)
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1
IMPORTANT
Before you start please read the following instructions carefully.
1. This assignment forms part of the formal assessment for this module. If
you fail to reach the required standard for the assignment then you will be
allowed to resubmit but a resubmission will only be eligible for a Pass
grade, not a Merit or Distinction.
You should therefore not submit the assignment until you are reasonably
sure that you have completed it successfully. Seek your tutor's advice if
unsure.
2. Ensure that you indicate the number of the question you are answering.
3. Make a copy of your answers before submitting the assignment.
4. Complete all details on the front page of this TMA and return it with
the completed assignment including supporting calculations where
appropriate. The preferred submission is via your TUOL(E) Blackboard
account:
https://eat.tees.ac.uk
5. Your tutor’s comments on the assignment will be posted on Blackboard.

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Assessment Criteria
This assignment takes the form of a design exercise to an engineering problem
concerning a digital system. The assignment forms Element 3 of the module’s
assessment criteria that covers in part Learning Outcomes 1, 2, 3 and 4 as
indicated below.
MODULE LEARNING OUTCOMES
Knowledge and Understanding
1. Demonstrate an understanding of a variety of electronic circuits including
power supplies, operational amplifier circuits and digital logic circuits.
Cognitive and Intellectual Skills
2. Choose appropriate circuit components for the design of electronic circuits.
Practical and Professional Skills
3. Build, simulate and test simple electronic circuits.
Key Transferable Skills
4. Demonstrate the application of numerical skills to the solution of problems
relating to digital and analogue devices and circuits.
PASS MERIT
Criteria in excess of the pass
grade.
DISTINCTION
Criteria in excess of the
merit grade.
Learning outcomes are
satisfied as evidenced by
substantially correct
understanding of the
operation and application of
simple operational amplifier
circuits.
The transfer of competence
gained in one situation to
related but unfamiliar
circumstances.
The ability to integrate
knowledge from two or
more topic areas to solve a
significantly more complex
problem.

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Refer to the tables at the end of the TMA when answering Questions 1 and 2.
1. FIGURE 1 shows an ALS logic circuit. Estimate:
(a) the current IOL
0.4mA as Output from gate. According to INTERFACING LOGIC
FAMILIES Table mentioned in the end of the document
(b) the delay in a 1-to-0 transition at one of the inputs of GATE 1
appearing as an effect at the output of GATE 5.
Propagation delay of one single gate is 4ns. For change in input at
GATE 1 to reflect on output at GATE 5, needs three propagation
delays. So total time is 12ns.
(c) the total power consumed by the circuit in a quiescent state.
Each gate has power consumption of 1mW. Total of 5 GATES will
consume 5mW of power.
2
1
IOL
1 11 4
1 5
1
3
1
FIG. 1

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2. (a) Explain with the aid of sketches and by using an example of a
specific logic family, what is meant by the term ‘noise immunity’.
The signals in gates are propagated and acknowledged based on their
Voltage levels. There is limit where a certain Maximum Voltage is
counted as 0 beyond which it would not be taken as 0 signal.
Similarly there is a minimum Voltage that must appear at input to be
counted as 1. Any Voltage below that level will not get counted as 1.
(05_digital_circuitry.pdf)
The outputs from a gate must confirm to these voltage levels.
However there might be some slight change in actual voltage levels
that appear of input of next Gate. The amount of Voltage fluctuation
that can be handled by a circuit in these expected voltage levels is
called noise immunity of that circuit or Gate.
Like in Diagram the Blue area is the indicator of noise immunity of
the circuit.
(b) Explain, if any, the problems associated with interfacing the logic
families of the circuits of FIGURE 2(a) and of FIGURE 2(b). For
each circuit, if there is a problem of interfacing, give a remedy.

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+5 V +5 V
7404 TTL
(a)
4049B CMOS
Interfacing of TTL to CMOS needs following 4 conditions to be satisfied:
VOH (TTL) ≥ VIH(CMOS)
VOL (TTL) ≤ VIL(CMOS)
-IOH (TTL) ≥ IIH(CMOS)
IOL (TTL) ≥ -IIL(CMOS)
The Current levels given in the datasheet confirm the required current conditions are met
when interfacing two families. The Two voltage conditions are however not satisfied. Only
the Low voltage levels are satisfied. The Output High Voltage of the TTL is far less than the
required Minimum voltage. To get the TTL drive a CMOS, a pull up resistor is required that
allows CMOS input to connect to supply voltage. The pull up resistance should be such that
Sink Current in TTL when input is low is within limits of TTL logic.
+5 V +5 V
4049B CMOS 7404 TTL
(b)
When interfacing the CMOS to a TTL circuit, the following 4 conditions need to be satisfied:
VOH (CMOS) ≥ VIH(TTL) 4.95 > 2.0
VOL (CMOS) ≤ VIL(TTL) .05 < 0.8
– IOH (CMOS) ≥ IIH(TTL) 0.51mA > 40uA
IOL (CMOS) < – IIL(TTL) 0.51mA < 1.6mA
Given data in the datasheet, confirms the ability of CMOS driver to provide sufficient Voltage levels to
count as logic 1 or 0 at the input of TTL device. Both limits are well within range of the required
values. The Current requirements of the driver also needs to be considered in this case. The current
for logic 1 is sufficiently large current for logic 0 is also well beyond maximum value allowed by TTL. So
device can connect directly without any other component.

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3. The block diagram of FIGURE 3 shows a three-stage asynchrononous
counter that is used to count a series of randomly occurring input pulses.
The ‘Q’ outputs of the counter are used to drive a logic circuit that gives
the output shown in TABLE 1.
(a) Design the counter using type D flip-flops and simulate your design
in PSpice, producing waveforms to confirm the circuit’s operation.
The circuit is an asynchronous UP counter using 3 D flip flops.
Initially a logic 0 is applied to the PRE pins of the flops. This resets
all flip flops. Then Inverted output of each flip flop is connected to
the input of the same flip flop. This helps toggle the flip flop in each
input clock. The asynchronous impulse input is used as clock to drive
the D flip flop. Output of the First stage is used as input clock for the
second clock. This makes a 3 bit asynchronous counter. The results
are available as Q1, Q2 and Q3. The same is visible in waveform
shown below.

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(b) Design the logic circuit to realise the desired ABCD outputs and
simulate your design in PSpice, again producing waveforms to
demonstrate the circuit’s operation.
The given circuit can be designed based on this truth table
Output from Counter Output from Circuit
Q3 Q2 Q1 A B C D
0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 1 1
0 1 1 0 1 1 1
1 0 0 1 1 1 1
1 0 1 1 1 1 0
1 1 0 1 1 0 0
1 1 1 1 0 0 0
Solving for the logic using K-Map
Q2Q1
Q3 00 01 11 10
0 0 0 0 0
1 1 1 1 1
A = Q3
Q2Q1

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Q3 00 01 11 10
0 0 0 1 0
1 1 1 0 1
B = Q3Q2Q1’ + Q3’Q2Q1 + Q3Q2’
Q2Q1
Q3 00 01 11 10
0 0 0 1 1
1 1 1 0 0
C = Q3Q2’ + Q3’Q2
Q2Q1
Q3 00 01 11 10
0 0 1 1 1
1 1 0 0 0
D = Q3Q2’Q1’ + Q3’Q2’Q1 + Q3'Q2
Based on the equations above, we can design the circuit as shown below:

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Logic
1
0
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In
Counter
t
Q1 Q2 Q3
A B C D
FIG. 3
Input pulse D C B A
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 1 1 1
4 1 1 1 1
5 1 1 1 0
6 1 1 0 0
7 1 0 0 0
8 0 0 0 0
9 0 0 0 1
etc
TABLE 1

1
1
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COMPARING LOGIC FAMILIES
Performance Specifications
Typical Single-Gate Performance Specifications
Family
Propagation
Delay (ns)
Power
Dissipation (mW)
Speed-Power
Product
pW-s (picowatt-seconds)
74 10 10 100
74S 3 20 60
74LS 9 2 18
74ALS 4 1 4
74F 2.7 4 11
4000B (CMOS) 105 1 at 1 MHz 105
74HC (CMOS) 10 1.5 at 1 MHz 15
INTERFACING LOGIC FAMILIES
Worst-Case Values for Interfacing Considerations for Vsupply of 5.0 V
Parameter 4000B CMOS 74HCMOS 74HCTMOS 74TTL 74LSTTL 74ALSTTL
VIH (min) (V) 3.33 3.5 2.0 2.0 2.0 2.0
VIL (max) (V) 1.67 1.0 0.8 0.8 0.8 0.8
VOH (min) (V) 4.95 4.9 4.9 2.4 2.7 2.7
VOL (max) (V) 0.05 0.1 0.1 0.4 0.4 0.4
IIH (max) (μA) 1 1 1 40 20 20
IIL (max) (μA) –1 –1 –1 –1600 –400 –100
*IOH (max) (mA) –0.51 –4 –4 –0.4 –0.4 –0.4
*IOL (max) (mA) 0.51 4 4 16 8 4
*The conversion is that current flowing into a gate terminal is positive and that flowing out is negative.

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