Cache Configurations Analysis

This assignment delves into the workings of three distinct cache configurations (C1, C2, and C3). It presents a memory address sequence and analyzes the corresponding tag bits, index bits, block offset bits, and hit/miss results for each configuration. The focus is on understanding how variations in block offsets influence the index field and overall cache performance. Additionally, the assignment specifies the details of each configuration's index entries and byte offsets.

Computer Architecture 1
The table below depicts the index bits, tag bits, block offset bits and hit/miss results of the three
cache configurations:
Memory
address
sequence
Binary
address bits
Tag bits Index bits Hit/Miss
C1 C2 C3 C1 C2 C3 C1 C2 C3
6 000 00 110 000 001 00 0
214 110 10 110 110 101 10 0
175 101 01 111 101 011 01 1
214 110 10 110 110 101 10 0
6 000 00 110 000 001 00 0
84 010 10 100 010 101 10 0 H H
65 010 00 001 010 000 00 1 H H H
174 101 01 110 101 011 01 0
64 010 00 000 010 000 00 0
105 011 01 001 011 010 01 1
85 010 10 101 010 101 10 1 H H
215 110 10 111 110 101 10 1
In summary, the difference between C1, C2 and C2 are the block- offsets which affects the index
field and though they are all of the same capacity, the tag field remains unchanged for C2 and C3

Computer Architecture 2
C1: Index: (8 entries); byte offset: 1:0 (1 word/block)
C2: Index: (8 entries); byte offset: 2:0 (2 word/block)
C3: Index: (2 entries); byte offset: 1:0 (1 word/block)
References
Anderson, J. R. (2013). The architecture of cognition. Psychology Press.
Jacobi, C., Slegel, T., & Greiner, D. (2012, December). Transactional memory architecture and
implementation for IBM System z. In Microarchitecture (MICRO), 2012 45th Annual
IEEE/ACM International Symposium on (pp. 25-36). IEEE.